Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.

A redundant sensor fabric in an autonomous vehicle may include receiving, by a processing unit, sensor data from a first sensor of a plurality of sensors associated with a same sensing space of the autonomous vehicle; detecting a fault associated with the first sensor; establishing, via a switched fabric, a communications path between the processing unit and a second sensor of the plurality of sensors; and receiving, by the processing unit, sensor data from the second sensor instead of the first sensor.

Provided are a computer program product, system, and method for generating a health condition message on a health condition detected at a first server to send to a host system accessing the first server. A determination is made of a health condition with respect to access to a first storage. A determination is made of an estimated Input/Output (I/O) delay to access the first storage resulting from the determined health condition. A health condition message is generated indicating the estimated I/O delay. The health condition message is transmitted to the host system, wherein the host system uses the estimated I/O delay to determine whether to perform a swap operation to redirect host I/O requests to data from the first server to a second server.

An input/output (I/O) device for a distributed modular I/O system includes a base adapted to be connected to an associated support structure. A terminal block is connected to the base and includes a plurality of wiring connections adapted to be connected to field wiring of an associated controlled system. The I/O device further includes first and second I/O modules each including a plurality of removable single-channel I/O submodules that are each releasably connected to the base and each configured for a select I/O operation for input and output of data relative to the associated controlled system. One or more pairs of the single-channel I/O submodules can be configured to be redundant within or between the first and second I/O modules. Each of the single-channel I/O submodules is operatively connected to wiring connections of the terminal block through the base. The I/O device further includes first and second network switches connected to the base. The first and second network switches are adapted to be respectively connected to first and second backplane circuits. The I/O device further includes first and second system modules connected to the base and each respectively connected to both of the first and second network switches. The first and second system modules are also each respectively operatively connected to all of the removable single-channel I/O submodules of both of the first and second I/O modules such that the first and second system modules control communication of I/O data between the first and second network switches and the single-channel I/O submodules.

Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.

Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.

An input/output (I/O) device for a distributed modular I/O system includes a base adapted to be connected to an associated support structure. A terminal block is connected to the base and includes a plurality of wiring connections adapted to be connected to field wiring of an associated controlled system. The I/O device further includes first and second I/O modules each including a plurality of removable single-channel I/O submodules that are each releasably connected to the base and each configured for a select I/O operation for input and output of data relative to the associated controlled system. One or more pairs of the single-channel I/O submodules can be configured to be redundant within or between the first and second I/O modules. Each of the single-channel I/O submodules is operatively connected to wiring connections of the terminal block through the base. The I/O device further includes first and second network switches connected to the base. The first and second network switches are adapted to be respectively connected to first and second backplane circuits. The I/O device further includes first and second system modules connected to the base and each respectively connected to both of the first and second network switches. The first and second system modules are also each respectively operatively connected to all of the removable single-channel I/O submodules of both of the first and second I/O modules such that the first and second system modules control communication of I/O data between the first and second network switches and the single-channel I/O submodules.

A redundant sensor fabric in an autonomous vehicle may include receiving, by a processing unit, sensor data from a first sensor of a plurality of sensors associated with a same sensing space of the autonomous vehicle; detecting a fault associated with the first sensor; establishing, via a switched fabric, a communications path between the processing unit and a second sensor of the plurality of sensors; and receiving, by the processing unit, sensor data from the second sensor instead of the first sensor.

A method is provided for a hyper-converged storage-compute system to implement an active-active failover architecture for providing Internet Small Computer System Interface (iSCSI) target service. The method intelligently selects multiple hosts to become storage nodes that process iSCSI input/output (I/O) for a target. The method further enables iSCSI persistent reservation (PR) to handle iSCSI I/Os from multiple initiators.

Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.