Systems and methods for preventing loss of audio during calls to and from a vehicle. In particular, systems and methods are provided for preventing the loss of audio for calls during an audio bus failure. Vehicles include interior microphones and speakers, which are connected via an audio bus. In some examples, the audio bus also includes other components such as a mixer, a transceiver, one or more cellular modems, an audio input module, and a digital signal processor. Using the audio bus, microphone input is beamformed and mixed and transmitted over a cellular network to a call recipient. Sound received back from the call recipient is received at the audio bus and transmitted to the vehicle via one or more speakers coupled to the audio bus. In some instances, the audio bus can fail, and alternative call procedures can be used to contact a remote advisor or other call recipient.

Systems and methods for preventing loss of audio during calls to and from a vehicle. In particular, systems and methods are provided for preventing the loss of audio for calls during an audio bus failure. Vehicles include interior microphones and speakers, which are connected via an audio bus. In some examples, the audio bus also includes other components such as a mixer, a transceiver, one or more cellular modems, an audio input module, and a digital signal processor. Using the audio bus, microphone input is beamformed and mixed and transmitted over a cellular network to a call recipient. Sound received back from the call recipient is received at the audio bus and transmitted to the vehicle via one or more speakers coupled to the audio bus. In some instances, the audio bus can fail, and alternative call procedures can be used to contact a remote advisor or other call recipient.

A method, system and computer program product are provided for implementing cable failover in multiple cable Peripheral Component Interconnect Express (PCIE) IO interconnections to an external IO enclosure. System firmware is provided for implementing health check functions for the PCIE IO interconnections to identify a faulted low byte cable. A cable failover mechanism recovers a PCI link to the external IO enclosure. A multiplexer logic is provided between the PCIE host bridge (PHB) and the cable connected to the IO enclosure to perform a full lane reversal of the PCIE lanes.

A device, system, and/or method includes an internal circuit configured to perform at least one function, an input-output terminal set and a repair circuit. The input-output terminal set includes a plurality of normal input-output terminals connected to an external device via a plurality of normal signal paths and at least one repair input-output terminal selectively connected to the external device via at least one repair signal path. The repair circuit repairs at least one failed signal path included in the normal signal paths based on a mode signal and fail information signal, where the mode signal represents whether to use the repair signal path and the fail information signal represents fail information on the normal signal paths. Using the repair circuit, various systems adopting different repair schemes may be repaired and cost of designing and manufacturing the various systems may be reduced.

Examples of techniques for hardware assisted data protection are disclosed. In one example implementation according to aspects of the present disclosure, a method may include receiving a read data record comprising at least one memory write, the read data record having an associated cyclic redundancy check (CRC). The method may further include calculating, by a hardware module, an expected CRC for the read data record. Additionally, the method may include comparing the expected CRC to a known CRC stored in a known CRC data store. Finally, the method may include authenticating the read data record when the expected CRC matches a corresponding known CRC.

Examples of techniques for hardware assisted data protection are disclosed. In one example implementation according to aspects of the present disclosure, a method may include receiving a read data record comprising at least one memory write, the read data record having an associated cyclic redundancy check (CRC). The method may further include calculating, by a hardware module, an expected CRC for the read data record. Additionally, the method may include comparing the expected CRC to a known CRC stored in a known CRC data store. Finally, the method may include authenticating the read data record when the expected CRC matches a corresponding known CRC.

A method, system and computer program product are provided for implementing cable failover in multiple cable Peripheral Component Interconnect Express (PCIE) IO interconnections to an external IO enclosure. System firmware is provided for implementing health check functions for the PCIE IO interconnections to identify a faulted low byte cable. A cable failover mechanism recovers a PCI link to the external IO enclosure. A multiplexer logic is provided between the PCIE host bridge (PHB) and the cable connected to the IO enclosure to perform a full lane reversal of the PCIE lanes.

A method, system and computer program product are provided for implementing cable failover in multiple cable Peripheral Component Interconnect Express (PCIE) IO interconnections to an external IO enclosure. System firmware is provided for implementing health check functions for the PCIE IO interconnections to identify a faulted low byte cable. A cable failover mechanism recovers a PCI link to the external IO enclosure. A multiplexer logic is provided between the PCIE host bridge (PHB) and the cable connected to the IO enclosure to perform a full lane reversal of the PCIE lanes.

A processing device includes a transmitter, a difference amplifier, and a data detector. A first output buffer of the transmitter receives data and has a first output coupled to a channel that is designed to have a first impedance value, but that has a second impedance value that which may or may not be equal to the first impedance value. A second output buffer of the transmitter receives the data and has an output coupled to a circuit that has the first impedance. The difference amplifier has inputs coupled to the outputs of the first and second output buffers. The data detector is coupled to an output of the difference amplifier. The data processing device operates in a test operation mode to provide test data to the first and second output buffers and to determine whether the second impedance is equal to the first impedance based on information from the data detector.

Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.