Data is sent from a memory buffer device to a host device over a link. An error in the data is determined. A read response cancellation signal is sent to the host device to indicate the error to the host device, where the read response cancellation signal is to be sent subsequent to the data being sent from the memory buffer device to the host device.

An example system includes a slave processor and a master processor. The master processor is configured to communicate with the slave processor over a digital communication link in a first mode, and over an analog communication link in a second mode. A method is also disclosed.

Embodiments are generally directed to a protocol aware testing engine for high speed link integrity testing. An embodiment of a processor includes a processing core for processing data; and a protocol aware testing engine, wherein the protocol aware testing engine includes a protocol aware packet generator to generate test packets in compliance with an IO protocol, and a packet aligning and checking unit to align test packets generated by the packet generator with returned test packets and to compare the generated test packets with the returned data packets.

An input and output module transmits and receives data via a data line. The input and output module includes a protocol machine for a security protocol for data transfer and a clock. The protocol machine and instructions for clock processing are stored as sequence control in a read-only memory of the input and output module.

A memory system includes a controller configured to transfer first data for a program operation, and a memory device configured to perform an error check operation for determining whether second data received from the controller are equal to the first data and the program operation for storing the first data.

A method for determining a two wire open fault on a two wire communications bus including determining a threshold in response to a first data from a first electronic control unit and a second data received from a second electronic control unit via the two wire communications bus, wherein the first data includes a first plurality of dominant bits and a first plurality of recessive bits and the second data includes a second plurality of dominant bits and a second plurality of recessive bits, determining a current network health indicator in response to a third data from the first electronic control unit having a third plurality of dominant bits and a third plurality of recessive bits, and generating a double wire open fault error report in response to the current network health indicator exceeding the threshold.

A method is provided to detect and handle failures in the communication in a network, including a sender (201, 203) and a receiver (202, 501, 502, 503), where communication between the sender and the receiver is message-oriented. The method includes: (a) the sender sending a message (M101, M101-C, M102-C) to the receiver; (b) the sender monitoring the transmission process of the message inside the sender and/or monitoring the message; (c) the sender executing a correctness check of (i) the message, e.g., its contents, and/or (ii) the transmission process of the message inside the sender; and (d) after the correctness check(s) has/have been completed, the sender informs the receiver of the result of the correctness check(s), wherein (e) the receiver of the message marks the message as being faulty and/or discards the message if the result of a correctness check indicates that the message and/or transmission process is faulty.

In a data processing device including two sets of circuit pairs which are respectively duplicated in two clock domains which are asynchronous to each other, an asynchronous transfer circuit that transfers a payload signal is provided between the two sets of circuit pairs. The asynchronous transfer circuit includes two sets of a pair of bridge circuits which are respectively connected to the two sets of circuit pairs, and asynchronously transfers the payload signal and a control signal indicating a timing at which the payload signal is stable on a reception side. The two sets of a pair of bridge circuits and the payload signals can be duplicated, but the control signal is not duplicated, and the received payload signal is used for timing control to supply an expected same time difference, to the pair of duplicated circuits. This enables asynchronous transfer between circuits duplicated in the asynchronous clock domains.

A method for determining a two wire open fault on a two wire communications bus including determining a threshold in response to a first data from a first electronic control unit and a second data received from a second electronic control unit via the two wire communications bus, wherein the first data includes a first plurality of dominant bits and a first plurality of recessive bits and the second data includes a second plurality of dominant bits and a second plurality of recessive bits, determining a current network health indicator in response to a third data from the first electronic control unit having a third plurality of dominant bits and a third plurality of recessive bits, and generating a double wire open fault error report in response to the current network health indicator exceeding the threshold.

A first server of a storage controller is configured to communicate with a host via a first bus interface, and a second server of the storage controller is configured to communicate with the host via a second bus interface. Data is written from the host via the first bus interface to a cache of the first server and via the second bus interface to a non-volatile storage of the second server. The data stored in the cache of the first server is periodically compared to the data stored in the non-volatile storage of the second server.