Examples may include intercepting packets outputted from a primary virtual machine (PVM) hosted by a first server and converting one or more fields of protocol headers for each intercepted packet such that output-packet-similarity may be increased between the PVM outputted packets and packets outputted by a secondary virtual machine (SVM) hosted by a second server.

A circuit is provided that has three clock sources, a first processing unit connected to the first clock source, a second processing unit connected to the second clock source, and an input unit. The first processing unit has a first logic circuit and a first memory circuit connected to the first logic circuit, wherein a first set of instructions, which is designed to implement a first control program when executed by the first logic circuit, is stored in the first memory circuit, wherein the first clock source specifies a clock timing of the execution of the first set of instructions. The second processing unit has a second logic circuit and a second memory circuit connected to the second logic circuit, wherein a second set of instructions, which is designed to implement a second control program when executed by the second logic circuit, is stored in the second memory circuit.

Fire-prevention control unit including several circuit boards and a dedicated communication bus for communication between the circuit boards, the circuit boards including at least one processing board, at least one input board and at least one output board. The at least one processing board is intended to process input data received from the at least one input board and to generate commands to send to the at least one output board, the at least one input board and the at least one output board being intended to communicate with one or more devices to be monitored or controlled. Each circuit board has two identical and physically distinct functional logic units, the functional logic units being adapted to perform the same function, each functional logic unit having a unit for direct communication with the communication bus according to a configurable architecture.

A computer interlocking system includes: a first sub-system and a second sub-system that have a same structure and function, where the first sub-system and the second sub-system form a double 2-vote-2 architecture, respectively including a main control layer, a network layer, and a communication and execution layer; the network layer being configured to construct a communication network of a sub-system in which the network layer is located; the main control layer and the communication and execution layer in the first sub-system being respectively connected to a communication network of the first sub-system; and the main control layer and the communication and execution layer in the second sub-system being respectively connected to a communication network of the second sub-system.

A programmable electronic computer embedded in an avionics environment on board an aircraft for implementing at least one critical function and associated electronic device, method and computer program are disclosed. In one aspect, the electronic computer includes at least one control module configured to implement a respective critical function and configured to deliver at least one output data item associated with the critical function, and at least one monitoring module of a control module of another electronic computer. Each monitoring module configured to implement the same respective critical function as the one implemented by the monitored control module.

Methods, systems, and computer readable media for providing Byzantine fault tolerance (BFT) are disclosed. According to one method, a method for providing BFT occurs at a computing platform executing a BFT protocol, wherein the computing platform is acting as a leader participant of a round of the BFT protocol. The method comprising: receiving signed round-change messages from multiple participants in the round; broadcasting a signed lock message indicating that signed round-change messages have been received from a predetermined number of the participants in the round voting for a same candidate block; receiving signed commit messages from multiple participants in the round; and broadcasting a signed decide message indicating the candidate block is a finalized block after the predetermined number of the participants in the round have sent signed commit messages indicating the candidate block.

A method, executed by a computer, includes pairing a first core with a second core to form a first core group, wherein each core of the group has a plurality of functional units, transferring instructions received by the first core to the second core for execution via a first inter-core communication bus, and executing the instructions on the second core. A computer system and computer program product corresponding to the above method are also disclosed herein.

Systems and methods for command line voting are provided. Aspects include obtaining, by an output logic device, a plurality of memory blocks from a plurality of buffers, each of the plurality of memory blocks including two or more output commands generated from a processing circuit based on a sensor data input, generating, by a hash function, a hash value for each of the plurality of memory blocks, comparing the hash value for each of the plurality of memory blocks to determine an output memory block from the plurality of memory blocks, and outputting, to an output hardware, the two more output commands from the output memory block.

A method to check for redundancy in two or more data lines comprises receiving data on a first data line, computing a first cyclic redundancy check (CRC) value on the data of the first data line, performing an exclusive OR (XOR) function on the first CRC value with a stored memory value, and updating the stored memory value with a result of the XOR function, and repeating on additional data lines until a last line is processed such that an error is indicated if a final stored memory value is not zero. An apparatus to check that two cores are operating in lockstep comprises a first core comprising a first data checker, a second core comprising a second data checker, and a lockstep checker to compare an output of the first data checker with an output of the second data checker.

A cache coherency protection system provides for data redundancy by sharing a cache coherence memory pool for protection purposes. The system works consistently across all communication protocols, yields improved data availability with potentially less memory waster and makes data availability faster in node/director failure scenarios. According to various embodiments, the cache coherency protection system may include a writer/requester director that receives a write request from host, a protection target director that is a partner of the writer/request director and a directory.