Provided is an image recognition processor. The image recognition processor includes a plurality of nano cores each configured to perform a pattern recognition operation and arranged in rows and columns, an instruction memory configured to provide instructions to the plurality of nano cores in a row unit, a feature memory configured to provide input features to the plurality of nano cores in a row unit, a kernel memory configured to provide a kernel coefficient to the plurality of nano cores in a column unit, and a difference checker configured to receive a result of the pattern recognition operation of each of the plurality of nano cores, detect whether there is an error by referring to the received result, and provide a fault tolerance function that allows an error below a predefined level.

Methods and apparatus for detecting that a processing node, in a network including a plurality of processing nodes, is reporting invalid results and for taking corrective actions in response to the detection are described.

A computer interlocking system includes: a first sub-system and a second sub-system that have a same structure and function, where the first sub-system and the second sub-system form a double 2-vote-2 architecture, respectively including a main control layer, a network layer, and a communication and execution layer; the network layer being configured to construct a communication network of a sub-system in which the network layer is located; the main control layer and the communication and execution layer in the first sub-system being respectively connected to a communication network of the first sub-system; and the main control layer and the communication and execution layer in the second sub-system being respectively connected to a communication network of the second sub-system.

A memory controller for controlling a memory device including a register for storing a plurality of parameters includes: a register information storage configured to store the plurality of parameters as a plurality of setting parameters, a register controller configured to provide the memory device with a parameter change command for requesting a selected parameter to be changed to a set value, and acquire, from the memory device, Cyclic Redundancy Check (CRC) calculation information on the plurality of parameters including the selected parameter, a CRC reference information generator configured to generate CRC reference information on the plurality of setting parameters including at least one setting parameter changed to the set value, and a CRC information comparator configured to determine whether an error is included in the plurality of parameters according to a comparison result between the CRC calculation information and the CRC reference information.

In part, disclosure relates to a method of regulating checkpointing in an active active fault tolerant system. The method includes receiving a request from a client through a network at a primary computer; copying, by the primary computer, the request from the client to a secondary computer; processing the request from the client, using the primary computer, to generate a primary computer result; processing the copy of the request from the client, using the secondary computer, to generate a secondary computer result; comparing the primary computer result and the secondary computer result to obtain a comparison metric; determining whether a minimum checkpoint interval has been met or exceeded; and if the minimum checkpoint interval has not been met or exceeded, delay initiating a checkpoint process from primary computer to secondary computer.

A noise estimation method includes decomposing a first matrix in which values of elements are represented by binary values into a coefficient matrix and a basic matrix, and estimating an element including noise among elements of the first matrix based on a result of comparison between a second matrix obtained by combining the coefficient matrix with the basic matrix and the first matrix.

In one embodiment, a method includes receiving data from one or more sensors associated with a vehicle; and receiving a message from a first processor. The message from the first processor includes a first control command for an actuator of the vehicle and a first certificate function. The method also includes receiving a message from the second processor. The message from the second processor includes a second control command for the actuator of the vehicle and a second certificate function. The method also includes computing a first certificate based on the first certificate function and the data; computing a second certificate based on the second certificate function and the data; determining a valid control signal based on an accuracy of the first second control command and second control command relative the first certificate and second certificate; and transmitting the valid control signal to the actuator of the vehicle.

A resilient system implementation in a network-on-ship with at least one functional logic unit and at least one duplicated logic unit. A resilient system and method, in accordance with the invention, are disclosed for detecting a fault or an uncorrectable error and isolating the fault. Isolation of the fault prevents further propagation of the fault throughout the system. The resilient system includes isolation logic or an isolation unit that isolates the fault.

Examples of the present disclosure relate to a method for anomaly response in a system on chip. The method comprises measuring a magnitude of a transient anomaly event in an operating condition of the system on chip. Based on the magnitude it is determined, for each of a plurality of components of the system on chip, an indication of susceptibility of that component to an anomaly event of the measured magnitude. Based on the determined indications of susceptibility for each of the plurality of components, an anomaly response action is determined. The method then comprises performing the anomaly response action.

A data processing system and methods for operating the same are disclosed. The method includes detecting a fault by comparing output signals from a first processing core and a second processing core, entering a safe mode based upon detecting the fault, completing transactions while in the safe mode, and determining whether the fault corresponds to a hard error. Based upon the fault corresponding to a hard error, one of processing cores is identified as a faulty core. The faulty core is inhibited from executing instructions and the other processing core is allowed to execute instructions.