A semiconductor package comprises a controlled voltage domain (CVD) and a master voltage domain (MVD). The MVD comprises an error-tolerance control (ETC) circuit. A basic execution block in the CVD generates a basic output value, based on at least two input values. A test execution block in the CVD generates a test digital root, based on digital roots of the input values. A digital root comparator in the CVD determines whether a digital root of the basic output value matches the test digital root. An error reporter in the CVD sends an error report to the ETC circuit in response to a determination that the digital roots do not match. The ETC may automatically adjust at least one power characteristic of the CVD, based on the error report. Other embodiments are described and claimed.

Certain embodiments may relate to providing increased storage capacity. For instance, a memory storage device may include a motherboard with an external communication interface. The memory storage device may also include a multiple solid-state drives coupled to the motherboard in communication with the external communication interface. Each of the plurality of solid-state drives may include a respective storage controller to manage the distribution of data during a write or read operation to a combination of a primary storage allocation and a redundant storage allocation. The redundant storage allocation may be included in the combination in response to detecting an error condition associated with at least a portion of the primary storage allocation.

In part, disclosure relates to a method of regulating checkpointing in an active active fault tolerant system. The method includes receiving a request from a client through a network at a primary computer; copying, by the primary computer, the request from the client to a secondary computer; processing the request from the client, using the primary computer, to generate a primary computer result; processing the copy of the request from the client, using the secondary computer, to generate a secondary computer result; comparing the primary computer result and the secondary computer result to obtain a comparison metric; determining whether a minimum checkpoint interval has been met or exceeded; and if the minimum checkpoint interval has not been met or exceeded, delay initiating a checkpoint process from primary computer to secondary computer.

A noise estimation method includes decomposing a first matrix in which values of elements are represented by binary values into a coefficient matrix and a basic matrix, and estimating an element including noise among elements of the first matrix based on a result of comparison between a second matrix obtained by combining the coefficient matrix with the basic matrix and the first matrix.

A system and method for protecting memory instructions against faults are described. The system and method include converting the slave instructions to dummy operations, modifying memory arbiter to issue up to N master and N slave global/shared memory instructions per cycle, sending master memory requests to memory system, using slave requests for error checking, entering master requests to the GM/LM FIFO, storing slave requests in a register, and comparing the entered master requests with the stored slave requests.

Internet-of-Things (IoT) controllers built using hardened industrial technologies which improve functionality and reliability, such as a fixed-loop model in which a loop is repeated with configured time periodicity where sensors are queried, sensor responses are read, configured calculations are performed, and logic rules are evaluated resulting in decisions made and outputs activated. A variety of redundancy techniques are utilized to provide continuous non-stop operation of IoT controllers to compensate for possible hardware and software failures. Robust IoT controller redundancy also allows periodic maintenance, software updates and security patch installation without shutting down the IoT controllers.

A geographical hot redundancy method includes: a first master computer transmitting to a second slave computer first input data items and a first execution context for the n.sup.th execution cycle of an application, first and second replicas being respectively executed on the first and second computers; execution of the first replica, updating the first execution context at the n.sup.th cycle end and transmission to the second computer; recovering the first input data items and the first execution context for the n.sup.th cycle as the second input data items and second execution context for the n.sup.th cycle; executing the second replica in the second execution context for the n.sup.th cycle, on the second input data items of the n.sup.th cycle, and updating the second execution context at the end of the n.sup.th cycle; and checking and verifying consistency by comparing first and second execution contexts at the n.sup.th cycle end.

A method for controlling operation of a medical device in a medical system having a medical device, a communication device including a remote control for the medical device, and a safety device adapted for data communication with the communication device. Input data is provided and processed by a first calculation to thereby provide a first calculation result. The input data is processed by a second calculation executed separately from first calculation to thereby provide a second calculation result. The first and second calculation results are compared. When the first and second calculation results are found equal, remote control of the medical device by a medical device application running on the communication device is allowed. When the first and second calculation results are found not equal, the medical device application running on the communication device for remote control of the medical device is prevented.

There is a need to detect faults on a path between a memory access circuit and a shared resource, faults in a logic circuit, and faults in the shared resource. A semiconductor device includes: a first memory access circuit; a second memory access circuit to check the first memory access circuit; a memory that outputs a memory address based on a first access address input from the first memory access circuit; a duplexing comparison circuit that compares the first access address with a second access address output from the second memory access circuit; a first address comparison circuit that compares the first access address with the memory address; and an error control circuit that outputs a control signal based on a comparison result from the duplexing comparison circuit and a comparison result from the first address comparison circuit.

An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error in the original instruction result.