A method for use in a computing system, comprising: storing, in a random-access memory, a working copy of a data item, the working copy of the data item being stored in the random-access memory by a first processor; registering, with a second processor, a respective address in the random-access memory where the working copy of the data item is stored; and correcting, by the second processor, any modifications to the working copy of the data item that are made after the working copy of the data item is stored in the random-access memory, the modifications being corrected in parallel with the first processor executing software based on the working copy of the data item.

A buffer (72), (74), (76), (60), (78), (20), (82-90) has a number of entries for buffering items associated with data processing operations. Buffer control circuitry (100) has a redundant allocation mode in which, on allocating a given item to the buffer, the item is allocated to two or more redundant entries of the buffer. On reading or draining an item from the buffer, the redundant entries are compared and an error handling response is triggered if a mismatch is detected. By effectively reducing the buffer capacity, this simplifies testing for faults in buffer entries.

A method codes a controller of a vehicle, wherein a set of vehicle parameters is coded into the controller as the coding parameters, and the set of vehicle parameters is additionally coded in another controller of the vehicle.

The disclosure provides a data processing device and method. The data processing device may include: a task configuration information storage unit and a task queue configuration unit. The task configuration information storage unit is configured to store configuration information of tasks. The task queue configuration unit is configured to configure a task queue according to the configuration information stored in the task configuration information storage unit. According to the disclosure, a task queue may be configured according to the configuration information.

A memory dispatcher, including an address decoder configured to decode a write address of received write data; a lockstep processor configured to generate, based on the decoded write address, primary and redundant memory write addresses and corresponding primary and redundant copies of the write data, if the decoded write address corresponds with a lockstep region of the memory; and a comparator coupled to the lockstep processor, and configured to compare the primary and redundant copies of the write data, and to compare the primary and redundant memory write addresses.

Embodiments of the present disclosure relate to a memory system, a memory controller, and a method of operating the memory system. According to the embodiments of the present disclosure, when result data obtained by derandomizing data included in a flag area is different from reference data after a random data unit is derandomized based on a seed, it is possible to detect an error occurring in the seed in a process of derandomizing the data and to prevent malfunction of firmware in advance by searching for a target seed and derandomizing the random data unit based on the target seed.

A processor, including a core; and a cache-coherent memory fabric coupled to the core and having a primary cache agent (PCA) configured to provide a primary access path; and a secondary cache agent (SCA) configured to provide a secondary access path that is redundant to the primary access path, wherein the PCA has a coherency controller configured to maintain data in the secondary access path coherent with data in the main access path.

In one aspect, an integrated circuit (IC) includes a multiplexor configured to receive data from a non-volatile memory and configured to receive data from a shadow memory, a shift register configured to generate a first signature from the data received from the non-volatile memory and configured to generate a second signature from the data received from the shadow memory; a signature storage configured to store the first signature; and a shadow memory checking controller configured to enable the multiplexor to send the data from the non-volatile memory to the shift register, and send a command to reload the shadow memory with data from the non-volatile memory in response to receiving an error flag. The IC also includes a comparator circuit configured to compare the first signature and the second signature and configured to send the error flag in response to the first signature and the second signature being different.

A method begins by a processing module dispersed storage error encoding a data segment to produce a set of encoded data slices and dispersed storage error encoding metadata associated with the data segment to produce a set of encoded metadata slices. The method continues with the processing module creating a set of data slice names for the set of encoded data slices and creating a set of metadata slice names based on the set of data slice names. The method continues with the processing module sending the set of encoded data slices and the set of data slice names to a dispersed storage network (DSN) memory for storage therein. The method continues with the processing module sending the set of encoded metadata slices and the set of metadata slice names to the DSN memory for storage therein.

Provided herein is a storage node of a distributed storage system and a method of operating the same. A memory controller may include a data controller configured to receive a write request and write data corresponding to the write request from a host, and configured to determine a physical address of a memory block in which the write data is to be stored based on chunk type information included in the write request, a memory control component configured to provide a program command for instructing the memory block to store the write data, the physical address, and the write data to the memory device, wherein the chunk type information is information about whether the write data indicates a type of data chunks or a type of coding chunks, the data chunks and the coding chunks being generated by the host performing an erasure coding operation on original data.