An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.

A method/device for recognizing a microprocessor hardware error, including comparing a first application's first result, running on a first microprocessor, with a second application's second result, running on the first/second microprocessor, with a microcontroller, providing comparison strategies, the hardware error being recognized as a function of the comparison, the microcontroller receiving a first message from the first microprocessor, and receiving a second message from the first microprocessor if the second application runs on the first microprocessor, or receives a first message from the second microprocessor if the second application runs thereon, the first message containing first comparison strategy information and first result information of a first function calculation, the second message containing second comparison strategy information and second result information of a second function calculation, the first and second strategy information being compared, the first and second result information being compared if the information about the comparative strategy coincides.

A method for recovering a clock signal from a data signal by using a clock recovery module is described. Edge timings of the data signal are accumulated. The edge timings accumulated are transformed into one reference bit period. A time offset for the reference bit period is determined. A reference clock signal is determined based on the time offset. The number of bits within a system clock of the clock recovery module is determined. The clock signal is recovered based on the reference clock signal and the number of bits. Further, a clock recovery module as well as a computer program are described.

An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.

The systems and methods described herein provide the ability to detect a clocking element fault within an IC device and switch to an alternate clock. In response to detection of a fault in a phase-lock-loop (PLL) clocking element, the device may switch to an alternate clock so that error reporting logic can make forward progress on generating error message. The error message may be generated within an Intellectual Property (IP) cores (e.g., IP blocks), and may send the error message from the IP core to a system-on-a-chip (SOC), such as through an SOC Functional Safety (FuSA) error reporting infrastructure. In various examples, the clocking error may also be output to a hardware SOC pin, such as to provide a redundant path for error indication.

Examples may include techniques for using a sample clock to measure a duty cycle by periodic sampling a target clock signal based on a prime number ratio of a reference clock frequency. The reference clock frequency used to set a measurement cycle time over which the duty cycle is to be measured. A magnitude of a duty cycle error as compared to a programmable target duty cycle is determined based on the measured duty cycle and the duty cycle is adjusted based, at least in part, on the magnitude of the duty cycle error.

A receiver device includes detection logic, an error counter, and an interrupt logic. The detection logic is to receive a first set of data frames and detect one or more frame errors in the first set of data frames. The error counter is to store a number of the one or more frame errors detected in the first set of data frames. The interrupt logic can be coupled to the error counter. The interrupt logic is to specify a period and compare the number of the one or more frame errors with a threshold number of frame errors during the period, where the interrupt logic is to indicate an interrupt responsive to the number of the one or more frame errors detected within the period satisfying the threshold number of frame errors.

Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation

A communication node (NODE) for connecting a fault-tolerant computer (FTC) to a real-time network (NET), wherein the node receives critical application data (HCAD1, HCAD2) from computation hosts (HOST) of the fault-tolerant computer, and the node is configured to forward the critical application data as node critical application data (NCAD) to the NET. The node includes at least a first end system (ES1), a second end system (ES2) and a switch (SW), and the switch includes at least a commander part (COM), a monitor part (MON) and a comperator part (COMP). The MON and the COMP may be integrated into an integrated part (MONC). The ES1 connects to the computation hosts or a subset thereof, and the ES2 connects to the computation hosts or a subset thereof. The ES1 connects to the COM, and the ES2 connects to the MON. The computation hosts or a subset thereof provide first host critical application data (HCAD1) to the ES1, and the computation hosts or a subset thereof provide second host critical application data (HCAD2) to the ES2. The ES1 is configured to forward the HCAD1 as first end system critical application data (ESCAD1) to the COM and the ES2 is configured to forward the HCAD2 as second end system critical application data (ESCAD2) to the MON. The COM is configured to forward the ESCAD1 as commander critical application data (CCAD) to the COMP at a pre-configured commander forwarding point in time (TCOM), and the MON is configured to forward the ESCAD2 as monitor critical application data (MCAD) to the COMP at a pre-configured monitor forwarding point in time (TMON). If the MON and the COMP are not integrated into an integrated part, then the COMP is configured to forward either the CCAD or the MCAD as node critical application data (NCAD), if and only if, the CCAD and the MCAD are identical and the COMP starts to receive the CCAD and the MCAD within an interval of configured length (SYNC-1). Alternatively, if the MON and the COMP are integrated into an integrated part (MONC), then the COM is configured to forward the ESCAD1 as NCAD to the NET. The switch includes an interception function (INTERCEPT) which is configured to (i) preempt an ongoing transmission of NCAD and/or (ii) prevent the transmission of NCAD, and the COMP is configured to activate the interception function if and only if the CCAD and the MCAD are not identical or the COMP does not start to receive the CCAD and the MCAD within SYNC-1.

A method of writing data into a memory device discloses utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank. The method further comprises writing a second plurality of data words into an error buffer, wherein the second plurality of data words comprises data words that are awaiting write verification associated with the memory bank. The method further comprises searching for a data word that is awaiting write verification in the error buffer, wherein the verify operation occurs in a same row as the write operation. The method also comprises determining if an address of the data word is proximal to an address for the write operation and responsive to a positive determination, delaying a start of the verify operation so that a rising edge of the verify operation occurs a predetermined delay after a rising edge of the write operation.