Patent classifications
G06F11/1683
MULTIPLEX SYSTEM
Each of a plurality of input units (110) outputs an input notification (104) at the input timing at which input data (101) is input and outputs input data at the synchronization timing which is the timing of the later one of the input timing and a timing at which an input notification is output from another input unit. Each of a plurality of computing units (120) starts a computation when input data output from an associated input unit is input.
System and method for reliable non-blocking messaging for multi-process application replication
A system, method, and computer readable medium for reliable messaging between two or more servers. The computer readable medium includes computer-executable instructions for execution by a processing system. Primary applications runs on primary hosts and one or more replicated instances of each primary application run on one or more backup hosts. The reliable messaging ensures consistent ordered delivery of messages in the event that messages are lost; arrive out of order, or in duplicate. The messaging layer operates over TCP or UDP with our without multi-cast and broad-cast and requires no modification to applications, operating system or libraries.
Software visible and controllable lock-stepping with configurable logical processor granularities
A processor is described. The processor includes model specific register space that is visible to software above a BIOS level. The model specific register space is to specify a granularity of a processing entity of a lock-step group. The processor also includes logic circuitry to support dynamic entry/exit of the lock-step group's processing entities to/from lock-step mode including: i) termination of lock-step execution by the processing entities before the program code to be executed in lock-step is fully executed; and, ii) as part of the exit from the lock-step mode, restoration of a state of a shadow processing entity of the processing entities as the state existed before the shadow processing entity entered the lock-step mode and began lock-step execution of the program code.
SOFTWARE VISIBLE AND CONTROLLABLE LOCK-STEPPING WITH CONFIGURABLE LOGICAL PROCESSOR GRANULARITIES
A processor is described. The processor includes model specific register space that is visible to software above a BIOS level. The model specific register space is to specify a granularity of a processing entity of a lock-step group. The processor also includes logic circuitry to support dynamic entry/exit of the lock-step group's processing entities to/from lock-step mode including: i) termination of lock-step execution by the processing entities before the program code to be executed in lock-step is fully executed; and, ii) as part of the exit from the lock-step mode, restoration of a state of a shadow processing entity of the processing entities as the state existed before the shadow processing entity entered the lock-step mode and began lock-step execution of the program code.
MULTIPROCESSOR SYSTEM
The present invention realizes a functional safety of a multiprocessor system without tightly coupling processor elements. When causing a plurality of processor elements to execute the same data processing and realizing a functional safety of the processor element, there is adopted a bus interface unit that performs control of performing safety measure processing when the non-coincidence of access requests issued from the processor elements has been fixed, and of starting access processing responding the access request when these access requests coincide with one another.
TECHNIQUES FOR IMPROVING OUTPUT-PACKET-SIMILARITY BETWEEN PRIMARY AND SECONDARY VIRTUAL MACHINES
Examples may include intercepting packets outputted from a primary virtual machine (PVM) hosted by a first server and converting one or more fields of protocol headers for each intercepted packet such that output-packet-similarity may be increased between the PVM outputted packets and packets outputted by a secondary virtual machine (SVM) hosted by a second server.
PROCESS SYNCHRONIZATION CONTROL SYSTEM AND PROCESS SYNCHRONIZATION CONTROL METHOD
In a process synchronization control system for performing a synchronization process of synchronizing a process among redundant channels, each of the channels includes an input unit; an output unit; a processing unit; a process execution timer which is used for executing a process in the channels; and a waiting time measurement timer which measures a waiting time in the synchronization process, in which the processing unit executes: a synchronization signal output process of outputting the synchronization signal to other channels at the start of the synchronization process; a synchronization signal input process of waiting for the synchronization signal input from the other channels until a predetermined waiting time by the waiting time measurement timer elapses; and a timer synchronization process of synchronizing the process execution timer if the synchronization signal of the other channels is input after the elapse of the waiting time.
Controlling non-redundant execution in a redundant multithreading (RMT) processor
In one embodiment, the present invention includes a method for controlling redundant execution such that if an exceptional event occurs, the redundant execution is stopped, non-redundant execution is performed in one of the threads until the exceptional event has been-resolved, after which a state of the threads is synchronized, and redundant execution is continued. Other embodiments are described and claimed.
Primary machine and fault-tolerant system
A primary machine includes a primary virtual machine including a synchronization information generator configured to generate and output synchronization information based on an instruction and a result of execution of the instruction, and a fault selector configured to determine a type of fault information generated when the instruction was executed. The primary VM changes operation depending on a result of the determination of the type of fault information.
Software visible and controllable lock-stepping with configurable logical processor granularities
A processor is described. The processor includes model specific register space that is visible to software above a BIOS level. The model specific register space is to specify a granularity of a processing entity of a lock-step group. The processor also includes logic circuitry to support dynamic entry/exit of the lock-step group's processing entities to/from lock-step mode including: i) termination of lock-step execution by the processing entities before the program code to be executed in lock-step is fully executed; and, ii) as part of the exit from the lock-step mode, restoration of a state of a shadow processing entity of the processing entities as the state existed before the shadow processing entity entered the lock-step mode and began lock-step execution of the program code.