A storage system in one embodiment comprises a storage controller and a plurality of storage devices comprising a plurality of memory portions. The storage controller is configured to monitor a plurality of servers for a failure event. The servers store a plurality of copies of the memory portions. The storage controller is further configured to mark as invalid a copy of a memory portion on a failed server, search for and identify a location on an operational server for storing a new version of the copy, and communicate the copy invalidity and the identified location to a client device using the memory portion. The client device is configured to generate the new version of the copy for storage on the operational server, and the storage controller receives a notification from the client device regarding whether the new version of the copy was generated and stored on the operational server.

A parallel processing system includes at least three processors operating in parallel, state monitoring circuitry, and state reload circuitry. The state monitoring circuitry couples to the at least three parallel processors and is configured to monitor runtime states of the at least three parallel processors and identify a first processor of the at least three parallel processors having at least one runtime state error. The state reload circuitry couples to the at least three parallel processors and is configured to select a second processor of the at least three parallel processors for state reload, access a runtime state of the second processor, and load the runtime state of the second processor into the first processor. Monitoring and reload may be performed only on sub-systems of the at least three parallel processors. During reload, clocks and supply voltages of the processors may be altered. The state reload may relate to sub-systems.

A networked database management system (DBMS) is disclosed. In particular, the disclosed DBMS includes a plurality of nodes, one of which is elected as a designated leader. The designated leader is responsible for maintaining an inventory of coding lines. A coding line spans all nodes in a cluster, and each node is assigned either data or parity. In addition, the designated leader maintains a pattern of parity rotation.

According to an aspect, a sever system includes a non-volatile storage device with a plurality of loadable configuration data and a configurable sever logic circuit configured responsive to a transfer of the loadable configuration data to perform a plurality of operations. The operations include mapping a plurality of module-level sever logic inputs to a plurality of module-specific sever logic functions as defined in the loadable configuration data. The module-level sever logic inputs are monitored by the configurable sever logic circuit based on the module-specific sever logic functions for a sever condition. A sever command to disconnect one or more outputs of a plurality of modules is triggered based on the module-specific sever logic functions and the module-level sever logic inputs.

The invention provides a memory management method, a memory storage device, and a memory control circuit unit. The method includes: recording an error bit number of each upper physical programming unit and an error bit number of each lower physical programming unit of each of the physical erasing units; determining whether a first physical erasing unit is a bad physical erasing unit according to distributions of the error bit numbers of the upper physical programming units and the lower physical programming units of the first physical erasing unit of the physical erasing units; and performing a data transfer operation on data in the first physical erasing unit if the first physical erasing unit is determined as the bad physical erasing unit.

There is disclosed a computing/data processing device comprising: a plurality of computing units, each computing unit comprising a computing resource; the computing device comprising at least three computing units, each computing unit comprising a/the same computing resource; each computing unit further comprising a computing unit access manager, each unit access manager being adapted to control access to the computing resource of the respective computing unit in response to at least one request; wherein, the computing unit access manager only allows a response to the at least one request if a majority of the computing units provide a same response to the at least one request; and wherein, the computing device comprising a network-on-a-chip, is provided on a chip and/or comprises an integrated chip (IC) or microprocessor. The IC beneficially comprises a Field-Programmable Gate Array (FPGA) device. In a preferred embodiment, the unit access manager controls access to the computing resource based on a token; the token comprising: a pointer to the respective computing resource, a set of rights relating to that computing resource, and a numerical representation of that computing resource.

Provided is an image recognition processor. The image recognition processor includes a plurality of nano cores each configured to perform a pattern recognition operation and arranged in rows and columns, an instruction memory configured to provide instructions to the plurality of nano cores in a row unit, a feature memory configured to provide input features to the plurality of nano cores in a row unit, a kernel memory configured to provide a kernel coefficient to the plurality of nano cores in a column unit, and a difference checker configured to receive a result of the pattern recognition operation of each of the plurality of nano cores, detect whether there is an error by referring to the received result, and provide a fault tolerance function that allows an error below a predefined level.

An arithmetic processing device includes: a memory controller that accesses a main storage device; a plurality of arithmetic processing cores that execute instructions; an instruction controller that controls execution of an access instruction to load and store data in the plurality of arithmetic processing cores from and to the main storage device; and a transfer controller that controls data transfer between the memory controller and the plurality of arithmetic processing cores in accordance with an instruction from the instruction controller.

The management computer has a memory which stores management information and management programs, and a CPU which refers to the management information and executes the management programs; the management information includes storage management information for allowing determination as to whether the plurality of storage resources can be paired in a redundant configuration, and couplable configuration management information for determining whether the plurality of storage resources and the plurality of server resources can be connected to each other; and when the CPU deploys a virtual machine, the CPU first determines, by reference to the storage management information, storage resources to be paired in a redundant configuration, then selects, by reference to the couplable configuration management information, server resources each of which can be connected to a respective one of the storage resources that are to be paired in a redundant configuration, and pairs the selected server resources in the redundant configuration.

According to an aspect, a sever system includes a non-volatile storage device with a plurality of loadable configuration data and a configurable sever logic circuit configured responsive to a transfer of the loadable configuration data to perform a plurality of operations. The operations include mapping a plurality of module-level sever logic inputs to a plurality of module-specific sever logic functions as defined in the loadable configuration data. The module-level sever logic inputs are monitored by the configurable sever logic circuit based on the module-specific sever logic functions for a sever condition. A sever command to disconnect one or more outputs of a plurality of modules is triggered based on the module-specific sever logic functions and the module-level sever logic inputs.