A system for database reversion is described. The system comprises: a database engine configured to host an active database; a log engine configured to generate transaction logs for transactions affecting the active database; a backup engine configured to create a backup data structure to allow for database reversion; and a memory buffer separate from the active database. A page in the active database has an associated page timestamp indicating a most recent update of the page in the active database. The database engine is configured to flush an updated copy of a page in the memory buffer to the active database. The backup engine is configured to, prior to the flush, store an image of the page in the active database to the backup data structure when the page in the active database is older than the time value related to the creation time of the backup data structure.

Described is a system and method that includes rerouting incoming data of a node to a first destination in response to determining that the node is in an unstable state, and evacuating data stored in the node to a second destination. Each destination of the first destination and the second destination comprises at least one of a persistent volume, a cloud storage, or another node in a mesh networkode.

An integrated circuit includes on-chip flash memory, a EEPROM, cache memory, and a repair controller. When a defective address is detected in the flash memory, data slotted to be stored at the defective address is stored in the EEPROM by the repair controller. The cache memory includes a content addressable memory (CAM) that checks read addresses with the defective memory address and if there is a match, the data stored in the EEPROM is moved to the cache so that it can be output in place of data stored at the defective location of the flash memory. The memory repair system does not require any fuses nor is the flash required to include redundant rows or columns. Further, defective addresses can be detected and repaired on-the-fly.

A transmitting computer for a vehicle is disclosed, and includes a command circuit, a monitor circuit, and a master circuit. The command circuit receives a real-time signal and executes a first set of instructions to analyze the real-time signal, and generates a plurality of command signals based on executing the first set of instructions. The monitor circuit receives the command signals and the real-time signal. The monitor circuit executes a second set of instructions to analyze the real-time signal and generates a plurality of replica signals based on executing the second set of instructions. The monitor circuit generates an initial reset command in response to determining an initial miscompare between one of the plurality of command signals and the plurality of replica signals. The master circuit is in communication with both the command circuit and the monitor circuit and receives an indication that the initial reset command is generated.

An integrated circuit includes on-chip flash memory, a EEPROM, cache memory, and a repair controller. When a defective address is detected in the flash memory, data slotted to be stored at the defective address is stored in the EEPROM by the repair controller. The cache memory includes a content addressable memory (CAM) that checks read addresses with the defective memory address and if there is a match, the data stored in the EEPROM is moved to the cache so that it can be output in place of data stored at the defective location of the flash memory. The memory repair system does not require any fuses nor is the flash required to include redundant rows or columns. Further, defective addresses can be detected and repaired on-the-fly.

The present invention realizes a functional safety of a multiprocessor system without tightly coupling processor elements. When causing a plurality of processor elements to execute the same data processing and realizing a functional safety of the processor element, there is adopted a bus interface unit that performs control of performing safety measure processing when the non-coincidence of access requests issued from the processor elements has been fixed, and of starting access processing responding the access request when these access requests coincide with one another.

An arithmetic processing device includes: a memory controller that accesses a main storage device; a plurality of arithmetic processing cores that execute instructions; an instruction controller that controls execution of an access instruction to load and store data in the plurality of arithmetic processing cores from and to the main storage device; and a transfer controller that controls data transfer between the memory controller and the plurality of arithmetic processing cores in accordance with an instruction from the instruction controller.

A method for redundant processing of data by at least two processing units is described. After a restart or reset, the first processing unit of the at least two processing units receives first portions of the data for processing from at least one second processing unit of the at least two processing units.

Methods and circuits are disclosed for error recovery in redundant processing systems. Respective instances of a software program are executed in lockstep on redundant processing circuits. Using a control circuit, in response to detecting a non-fatal error, an interrupt is generated and non-functioning ones of the processing circuits are disabled. The interrupt is serviced using the functional processing circuits operating in lockstep. In servicing the interrupt, a processing state of the processing circuits is stored and a reset of the processing circuits is triggered. Following the reset, the processing circuits are configured to operate in lockstep. The state of the processing circuits is restored to the stored processing state and a return from the interrupt is signaled. In response to the signaled return from interrupt, execution of the software program is resumed on the processing circuits in lockstep at a point at which the non-fatal error was detected.

A processor-implemented method, for continuing operation of a quorum based system is provided. The method detects a loss of quorum. A plurality of speculative configurations is created, whereby each speculative configuration is isolated from other speculative configurations in the quorum based system. Each speculative configuration continues to order requests during the creation of speculative configurations. The method selects and starts one of the plurality of speculative configurations as a new operational configuration. Ordered requests continue to the new operational configuration. The original configuration of the quorum based system is restarted in response to the plurality of speculative configurations not being isolated.