A method tests a plurality of devices, each device including a test chain having a plurality of positions storing test data. The testing includes comparing test data in a last position of the test chain of each of the devices. The test data in the test chains of the devices is shifted forward by one position. The shifting includes writing test data in the last position of a test chain to a first position in the test chain. The comparing and the shifting are repeated until the test data in the last position of each test chain when the testing is started is shifted back into the last position of the respective test chain. The plurality of devices may have a same structure and a same functionality.

The voter circuit and method determines a voted output among plural inputs each carrying circular data. To supply the voted output, a statistical average (e.g., mean or median) is computed by grouping the plural inputs into pairs, and for each pair generating a minimum angular difference by selecting the minimum of (a) the absolute difference between the pairs of inputs, and (b) the conjugate of the absolute difference between the pairs of inputs. The voted output is a statistical average generated from the minimum angular difference. The monitor circuit and method assesses validity among the plural inputs by comparing inputs in pairs, two-by-two, generating for each pair a minimum angular difference and comparing the difference to a threshold and persistence time is confirmed. The monitor declares an input invalid that is in disagreement with all other inputs paired against it.

Methods and systems for handling a single event upset. The methods include, and/or the systems include functionality for, receiving, from a monitored device, data at a first input of an initial state change device; detecting, based on receiving the data, a state change; asserting, based on detecting the state change, an initial state change device enable signal; transferring the first data from the first input to a first output of the initial state change device (which may be operatively connected to a second input of a state hold device); triggering, based on detecting the state change, a delay counter; making a determination that the delay period counted by the delay counter expired without receipt of an error detection signal; and based on the determination, asserting a state hold device enable signal to allow the data to pass from the second input to a second output of the state hold device.

A memory system includes a processing device (e.g., a controller implemented using a CPU, FPGA, and/or logic circuitry) and memory regions (e.g., in a flash memory or other non-volatile memory) storing data. The processing device receives an access request from a host system that is requesting to read the stored data. In one approach, the memory system is configured to: receive, from the host system over a bus, a read command to access data associated with an address in a non-volatile memory; in response to receiving the read command, access, by the processing device, multiple copies of data stored in at least one memory region of the non-volatile memory; match, by the processing device, data from the copies with each other; select, based on matching data from the copies with each other, first data from a first copy of the copies; and provide, to the host system over the bus, the first data as output data.

The method includes creating and sending a change request for a change to the system configuration of the hardware system by means of a first hardware component of the plurality of hardware components, receiving the change request by means of the further hardware components of the plurality of hardware components, checking the change request by means of the further hardware components for compatibility of the change request with the configuration of the particular receiving hardware component by using configuration data of the receiving hardware component, in the case that the requested change to the system configuration is compatible with the configuration of the receiving hardware component, generating and sending an approval of the change to the system configuration by means of the receiving hardware component, and in the case that an approval quorum of the hardware components that is necessary for consent is achieved, entering the requested change to the system configuration of the hardware system into the block chain, implementing the requested change to the system configuration in the hardware system.

To provide a microcontroller that suppresses increase of power consumption during debugging, a microcontroller according to the present invention includes a first signal processing circuit, a second signal processing circuit that performs signal processing in the same manner as the first signal processing circuit, a comparing circuit that compares a processing result of the first signal processing circuit and a processing result of the second signal processing circuit with each other, and outputs an error signal when an error is detected, a suppressing signal input unit that receives a suppressing signal for suppressing an operation of the second signal processing circuit and an operation of the comparing circuit, a suppressing circuit that receives the suppressing signal from the suppressing signal input unit and suppresses the operation of the second signal processing circuit and the operation of the comparing circuit, and a pseudo error signal output circuit that outputs a pseudo error signal in place of the error signal, when the operation of the second signal processing circuit and the operation of the comparing circuit are suppressed.

A computer interlocking system includes: a first sub-system and a second sub-system that have a same structure and function, where the first sub-system and the second sub-system form a double 2-vote-2 architecture, respectively including a main control layer, a network layer, and a communication and execution layer; the network layer being configured to construct a communication network of a sub-system in which the network layer is located; the main control layer and the communication and execution layer in the first sub-system being respectively connected to a communication network of the first sub-system; and the main control layer and the communication and execution layer in the second sub-system being respectively connected to a communication network of the second sub-system.

An improved blockchain implementation that uses proof-of-transfer to overcome the technical deficiencies of proof of work and proof-of-stake implementations is described herein. For example, the proof-of-transfer process may include elements of a single-leader election sortition, but modified to cause base chain cryptocurrency committed for the purposes of the sortition to be transferred to a burn address or at least one reward address.

Implementations of the present disclosure include setting, by a first consensus node, a timer that runs out before a timeout of a view change; sending, to a second consensus node, a request for one or more consensus messages missing by the first consensus node in response to the timer running out; receiving, from the second consensus node, the one or more consensus messages each digitally signed by a private key of a corresponding consensus node that generates the respective one or more consensus messages; and determining that a block of transactions is valid, if a quantity of commit messages included in the received one or more consensus messages is greater than or equal to 2f+1, where f is a maximum number of faulty nodes that is tolerable by the blockchain based on practical Byzantine fault tolerance.

Methods, systems, and computer readable media for providing Byzantine fault tolerance (BFT) are disclosed. According to one method, a method for providing BFT occurs at a computing platform executing a BFT protocol, wherein the computing platform is acting as a leader participant of a round of the BFT protocol. The method comprising: receiving signed round-change messages from multiple participants in the round; broadcasting a signed lock message indicating that signed round-change messages have been received from a predetermined number of the participants in the round voting for a same candidate block; receiving signed commit messages from multiple participants in the round; and broadcasting a signed decide message indicating the candidate block is a finalized block after the predetermined number of the participants in the round have sent signed commit messages indicating the candidate block.