A method includes identifying multiple apportionments, where each apportionment identifies numbers of bit copies to be stored in at least one memory for at least some bits of a data value. The method also includes, for each apportionment, estimating a numerical error associated with use of the apportionment with a specified function, where the numerical error is estimated by creating errors in bit copies of multiple data values processed using the specified function. The method further includes combining portions of different ones of the apportionments having lower estimated numerical errors to create multiple derived apportionments. The method also includes, for each derived apportionment, estimating a numerical error associated with use of the derived apportionment with the specified function. In addition, the method includes selecting a final apportionment for use with the specified function, where the final apportionment includes or is based on at least one of the derived apportionments.

The disclosure relates to an apparatus and method for false pass detection in lockstep dual processing core systems, triple modular redundancy (TMR) systems, or other redundant processing systems. A false pass occurs when two processing cores generate matching data outputs, both of which are in error. A false pass may occur when the processing core are both subjected to substantially the same adverse condition, such as a supply voltage drop or a sudden temperature change or gradient. The apparatus includes processing cores configured to generate first and second data outputs and first and second timing violation signals. A voter-comparator validates the first and second data outputs if they match and the first and second timing violation signals indicate no timing violations. Otherwise, the voter comparator invalidates the first and second data outputs. Validated data outputs are used for performing additional operations, and invalidated data outputs may be discarded.

A voter-based method of controlling a redundancy is provided, including acquiring a processing element array in a target hardware, wherein the processing element array includes a plurality of processing elements, selecting a plurality of groups of processing elements from the processing element array so as to generate a voter set, wherein a corresponding voter is generated for each group of the plurality of groups of processing elements, and the corresponding voter configured to perform a voting operation in a redundancy control, acquiring, in response to a message indicating a fault state of a detected voter, a target voter from the voter set so as to replace the detected voter, and re-performing the voting operation in the redundancy control by using the target voter. An electronic device and a storage medium are further provided, which are implemented based on the processing element array of the target hardware.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing view change. One of the methods is to be implemented on a blockchain and performed by a first node of N nodes in a view change protocol. The method includes: multicasting a view change message to at least some of the N nodes; obtaining, respectively from at least Q second nodes of the N nodes, at least Q echo messages each comprising: a consistent current view known to the second node indicating a primary node designated among the N nodes, and a consistent current sequence number known to the second node, the current sequence number associated with a latest transaction or a latest block, the current sequence number is larger than a first sequence number known to the first node; and responsive to obtaining the at least Q echo messages, ending the view change protocol.

Integrated circuits such as application specific integrated circuits or programmable logic devices may include multiple copies of a same circuit together with a majority vote circuit in a configuration that is sometimes also referred to as multi-mode redundancy. An adder circuit may be coupled to these multiple copies and produce a carry-out signal and a sum signal based on signals received from the multiple copies. The carry-out signal of the adder circuit may provide the result of the majority vote operation. A logic exclusive OR gate may perform a logic exclusive OR operation between the sum signal and the carry-out signal, thereby generating an error signal. The error signal may indicate that one of the multiple copies produces an output that is different than the outputs produced by the other copies.

A control apparatus includes a first controller configured to generate control signals for controlling an engine or other machine, a second controller configured to generate the control signals for controlling the machine, a transfer circuit, and an arbiter circuit. The transfer circuit is coupled between the machine and the controllers, and is configured to switch from a first state, where the transfer circuit passes the control signals from the first controller to the machine, to a second state, where the transfer circuit passes the control signals from the second controller to the machine, responsive to receiving a first failure signal from the first controller. The arbiter circuit includes three (or more) arbiters, and is configured to control the transfer circuit from the first state to the second state responsive to any two of the three arbiters generating second signals indicative of failure of the first controller.

The present disclosure discloses an arbitration processing solution when brain split occurs in cluster. The solution includes: receiving, by a quorum storage apparatus within a first refresh packet detection period, first master quorum node preemption requests sent by at least two quorum nodes in the cluster; sending, by the quorum storage apparatus, a first master quorum node preemption success response message to the initial master quorum node indicating that the initial master quorum node succeeds in master quorum node preemption when the first master quorum node preemption requests received within the first refresh packet detection period comprise the master quorum node preemption request sent by the initial master quorum node.

The present invention provides a microcontroller which can continue operation even at the time of a failure without making a memory redundant to suppress increase in chip area. The microcontroller includes three or more processors executing the same process in parallel and a storage device. The storage device includes a memory mat having a storage region which is not redundant, an address selection part, a data output part, and a failure recovery part. The address selection part selects a storage region in the memory mat on the basis of three or more addresses issued at the time of an access by the processors. The data output part reads data from the storage region in the memory mat selected by the address selection part. The failure recovery part corrects or masks a failure of predetermined number or less which occurs in the memory mat, the address selection part, and the data output part.

A computer-implemented method may comprise executing, by a first plurality of replicated state machines, a sequence of ordered agreements to make mutations to a data stored in a first data storage service of a first type and executing, by a second plurality of replicated state machines, the sequence of ordered agreements to make mutations to the data stored in a second data storage service of a second type. First metadata of the mutated data stored in the first data storage service may then be received and stored, as may second metadata of the mutated data stored in the second data storage service. A comparison of the stored first and second metadata may then be carried out when the data stored in the first data storage service that corresponds to the first metadata and the data stored in the second data storage service that corresponds to the second metadata have been determined to have settled according to the predetermined one of the sequence of ordered agreements. A selected action may then be carried out depending upon a result of the comparison.

Implementations of the present disclosure include setting, by a first consensus node, a timer that runs out before a timeout of a view change; sending, to a second consensus node, a request for one or more consensus messages missing by the first consensus node in response to the timer running out; receiving, from the second consensus node, the one or more consensus messages each digitally signed by a private key of a corresponding consensus node that generates the respective one or more consensus messages; and determining that a block of transactions is valid, if a quantity of commit messages included in the received one or more consensus messages is greater than or equal to 2f+1, where f is a maximum number of faulty nodes that is tolerable by the blockchain based on practical Byzantine fault tolerance.