Patent classifications
G06F11/2002
Adaptive private network with path maximum transmission unit (MTU) discovery process
Systems and techniques are described for a path maximum transmission unit (MTU) discovery method that allows the sender of IP packets to discover the MTU of packets that it is sending over a conduit to a given destination. The MTU is the largest packet that can be sent through the network along a path without requiring fragmentation. The path MTU discovery method actively probes each sending path of each conduit with fragmentation enabled to determine a current MTU and accordingly increase or decrease the conduit MTU. The path MTU discovery process is resilient to errors and supports retransmission if packets are lost in the discovery process. The path MTU discovery process is dynamically adjusted at a periodic rate to adjust to varying network conditions.
Managing VIOS failover in a single storage adapter environment
According to one exemplary embodiment, a method for VIOS failover in an environment with a physical storage adapter is provided. The method may include assigning the physical storage adapter to a first VIOS, wherein the physical storage adapter has I/O connectivity to at least one storage device. The method may include configuring a first I/O path between the first VIOS and a second VIOS. The method may include configuring a second I/O path from a client partition to the first VIOS, wherein the second I/O path is set as a primary I/O path. The method may include configuring a third I/O path from the client partition to the second VIOS. The method may include determining the first VIOS is inaccessible. The method may include unassigning the physical storage adapter from the first VIOS. The method may include assigning the physical storage adapter to the second VIOS.
Managing VIOS failover in a single storage adapter environment
According to one exemplary embodiment, a method for VIOS failover in an environment with a physical storage adapter is provided. The method may include assigning the physical storage adapter to a first VIOS, wherein the physical storage adapter has I/O connectivity to at least one storage device. The method may include configuring a first I/O path between the first VIOS and a second VIOS. The method may include configuring a second I/O path from a client partition to the first VIOS, wherein the second I/O path is set as a primary I/O path. The method may include configuring a third I/O path from the client partition to the second VIOS. The method may include determining the first VIOS is inaccessible. The method may include unassigning the physical storage adapter from the first VIOS. The method may include assigning the physical storage adapter to the second VIOS.
INTELLIGENT DATA PLANE ACCELERATION BY OFFLOADING TO DISTRIBUTED SMART NETWORK INTERFACES
A system for processing data, comprising a compute node having a first processor that is configured to receive a digital data message containing a request for computing services and to allocate processing resources on a private network as a function of the request. A smart network interface controller (NIC) management system operating on a second processor and configured to cause the second processor to select a smart NIC associated with the private network to allocate the smart NIC to the computing services. The smart NIC includes a processor that is configured to interface with a public network and to send and receive data over the public network associated with the computing services.
Node Anomaly Event Processing Method, Network Interface Card, and Storage Cluster
A node anomaly event processing method is applied to a network interface card in a storage device. The storage device further includes a plurality of nodes configured to manage a storage. The network interface card is communicatively connected to a first node in the plurality of nodes. When detecting an anomaly event related to the first node, the network interface card can actively send a notification message to a host to notify the host that an anomaly occurs on a path on which the first node is located, so that the host performs path switching.
MULTI-HOST ENVIRONMENT RESILIENCY
One or more aspects of the present disclosure relate to achieving resiliency and high availability in a multi-host environment. In embodiments, a plurality of Peripheral Component Interconnect Express (PCIe) links and network interface cards (NICs) controlled by a plurality of hosts in a multi-host environment is monitored. In addition, a fault condition is detected. For example, the fault condition includes at least an unexpected NIC reset, a PCIe link fault, or a server power cycle event. Further, traffic transmission over a network is controlled based on the fault condition.
SYSTEMS AND METHOD FOR ANOMALY DETECTION PIPELINE WITH FEW-SHOT LANGUAGE MODELS
A method may include: receiving a plurality of log-text examples from network devices and labels indicating if the log-text example is anomalous or not anomalous; identifying, from the log-text examples and labels, rules for weak annotation, and validation labels for a validation dataset and test labels for a test dataset; organizing log-text examples in the validation dataset into a plurality of time windows; concatenating log-text examples in each time window; providing the concatenated log-text examples and the rules for weak annotation to a weak annotation framework, to a LLM training dataset; training a LLM with the LLM training dataset; collecting runtime log-texts from the network devices for a period of time; concatenating the runtime log-texts for the period of time; and prompting the LLM for analysis with the concatenated log-texts, wherein the LLM outputs a response of anomaly or no anomaly and a confidence in the response.
Bi-directional controller area network communication system of multiple devices
A communication system for sub-devices from a first sub-device to an n.sup.th sub-device, which are connected to a main device through a communication line, includes a switch provided at each of both ends of the main device and the plurality of sub-devices to open and close the communication line, a termination resistor and a termination switch provided at each of both ends of the main device and the sub-devices to form one termination end of the communication line when the switch is opened, a first communication line sequentially connecting the main device to each of the sub-devices from the first sub-device to the n.sup.th sub-device, a second communication line directly connecting one end of the main device to one end of the n.sup.th sub-device, and a processor electrically connected to the switch and the termination switch to control opening/closing operations of the switch and the termination switch.
CONFIGURABLE DIE-TO-DIE LANE REPAIR IN MULTI-DIE SYSTEMS COUPLED USING LINK MACROS
Systems and methods for configurable die-to-die lane repair in multi-die systems are described. A multi-die system includes a first die and a second die, each of which comprises modular D2D link macros, where each of the modular D2D link macros has M data lanes. A method for configuring die-to-die lane repair includes forming repair groups having D data lanes spanning M data lanes, or fewer than M data lanes, associated with one or more modular D2D link macros, where D is independently configurable for each repair group. The method further includes, for each one of the repair groups designating R redundant lanes from among the D data lanes, where R is a positive integer independently configurable for each repair group, and where a location of each of the designated redundant lanes within a die floor plan associated with a respective repair group is independently configurable.
DYNAMICALLY RECONFIGURED REDUNDANT LANES IN A COMMUNICATION INTERFACE CIRCUIT BETWEEN CHIPLETS TO INCREASE REDUNDANCY WHEN THE PROBABILITY OF FAILURE FAVORS A PARTICULAR COMMUNICATION DIRECTION
An integrated circuit (IC) package including a first chiplet, a second chiplet, and a communication interface circuit coupling the first and second chiplets is disclosed. The communication interface circuit comprises main lanes wherein a first portion of which communicates information from the first chiplet to the second chiplet (i.e., first direction) and wherein a second portion of which communicates information from the second chiplet to the first chiplet (i.e., second direction). The communication interface circuit also comprises a plurality of redundant lanes wherein each of the redundant lanes are dynamically configurable to communicate in one of a first and a second direction.