Patent classifications
G06F11/2002
Identification of an alternate principal member port by a target device in a storage area network
Examples disclosed herein relate to identification of an alternate principal member port by a target device in a Storage Area Network (SAN). In some examples, a target device in a SAN may determine that a principal member port of a target driven peer zone on the target device is likely to fail based on diagnostic information related to the principal member port. The target driven peer zone may be configured in the SAN via the target device. In response to determining, the target device may identify an alternate principal member port on the target device. The target device may perform an action to indicate the alternate principal member port as the principal member port.
Network device
A network device may include a first forwarding board, a second forwarding board and an interface board. The interface board may include a control apparatus and a network interface chip. The control apparatus may form a first upstream packet flow which is sent to the first forwarding board via a first I/O bus and a second upstream packet flow which is sent to the second forwarding board via a second I/O bus using data packets received through the network interface chip from the exterior of the network device. The control apparatus may selectively connect one of a first downstream packet flow and a second downstream packet flow to the network interface chip through the network interface bus according to an active/standby state of the first forwarding board and the second forwarding board, wherein the first downstream packet flow is processed by the first forwarding board and received through the first I/O bus and the second downstream packet flow is processed by the second forwarding board and received through the second I/O bus.
Bus arbitration with routing and failover mechanism
In an embodiment of the invention, an apparatus comprises: a plurality of bus masters and a plurality of bus arbiters to support routing and failover, wherein each bus arbiter is coupled to a plurality of bus masters; and a central processing unit (CPU) coupled to at least one of the bus arbiters; wherein the CPU is configured to execute a firmware that chooses bus re-routing or failover in response to a bus failure. In another embodiment of the invention, a method comprises: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure. In yet another embodiment of the invention, an article of manufacture, comprises a non-transient computer-readable medium having stored thereon instructions that permit a method comprising: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure.
FENCE RANDOMIZATION WITH INTER-CHIP FENCING CONSTRAINTS
Fence randomization with inter-chip fencing constraints, including: receiving a fencing setup comprising one or more parameters for fencing a plurality of chips in a plurality of drawers; and selecting, based on the one or more parameters and one or more dependencies for implementing the one or more parameters, a subset of the plurality of chips for fencing, wherein the subset of the plurality of chips are selected at least partially randomly; generating a testing configuration indicating the selected subset of the plurality of chips.
System implemented on the basis of a field broadband bus architecture of industrial internet
The disclosure relates to a system implemented on the basis of a field broadband bus architecture of industrial internet, where this system is based upon a two-wire data transmission network widely applied in a traditional industry control system; multi-carrier orthogonal frequency division multiplexing technology is introduced to provide a large bandwidth above hundreds of megahertz; a design of a special frame structure, reasonable static and dynamic configurations of physical layer resource blocks, as well as a scheduling strategy of data services at medium access control layer, achieve proper mapping of transmission services to time slices; and a fast synchronized, real-time, high-speed, and reliable solution is provided with respect to the good performance, high reliability, strict real-time characteristic and high security required by a field broadband bus architecture of industrial internet.
REDUCING RECOVERY TIME OF AN APPLICATION
Examples provided herein describe a method for reducing recovery time for an application. For example, a first physical processor of a computing device may monitor, based on a first application instance of the application running in a first mode, for failure detection of the first application instance running on a first computing device. The first physical processor may determine that the first application instance is to be changed from the first mode to a second mode. Based on the determination, the first physical processor may validate that a second application instance can run in the first mode by performing a data integrity compliance check. Responsive to validating that the second application instance can run in the first mode, the first physical processor may facilitate running of the second application instance in the first mode.
Processor repair
A processor comprises a plurality of processing units, wherein there is a fixed transmission time for transmitting a message from a sending processing unit to a receiving processing unit, based on the physical positions of the sending and receiving processing units in the processor. The processing units are arranged in a column, and the fixed transmission time depends on the position of a processing circuit in the column. An exchange fabric is provided for exchanging messages between sending and receiving processing units, the columns being arranged with respect to the exchange fabric such that the fixed transmission time depends on the distances of the processing circuits with respect to the exchange fabric.
Device and system including adaptive repair circuit
A device, system, and/or method includes an internal circuit configured to perform at least one function, an input-output terminal set and a repair circuit. The input-output terminal set includes a plurality of normal input-output terminals connected to an external device via a plurality of normal signal paths and at least one repair input-output terminal selectively connected to the external device via at least one repair signal path. The repair circuit repairs at least one failed signal path included in the normal signal paths based on a mode signal and fail information signal, where the mode signal represents whether to use the repair signal path and the fail information signal represents fail information on the normal signal paths. Using the repair circuit, various systems adopting different repair schemes may be repaired and cost of designing and manufacturing the various systems may be reduced.
Coordination of spare lane usage between link partners
Various examples of techniques for identifying a corrupt data lane and using a spare data lane are described herein. Some examples include a system of coordinating spare lane usage between link partners. One such example comprises analyzing data from a link partner to identify a corrupt lane, and communicating the corrupt lane to the link partner, wherein the communication does not require sideband communication channel. In some embodiments, communicating the corrupt lane to the link partner comprises identifying a transmit lane corresponding to the corrupt lane, transmitting a set of data intended for a corresponding transmit lane using a spare data lane, and transmitting bad data to the link partner using the corresponding transmit lane.
Distributed computing system failure detection
A technology is described for detecting a failure of a distributed system component. An example method may include registering a declarative file that may identify a distributed computing cluster in a service provider environment and provide failure criteria used to detect a failure of a distributed system component included in the distributed computing cluster. Distributed system components included in the distributed computing cluster may then be identified using information included in the declarative file. A distributed system component included in the distributed computing cluster may then be queried according to query criteria provided by the declarative file and a failure state of the distributed system component included in the distributed computing cluster may be identified based in part on a result of querying the distributed system component.