A method is provided for a hyper-converged storage-compute system to implement an active-active failover architecture for providing Internet Small Computer System Interface (iSCSI) target service. The method intelligently selects multiple hosts to become storage nodes that process iSCSI input/output (I/O) for a target. The method further enables iSCSI persistent reservation (PR) to handle iSCSI I/Os from multiple initiators.

A memory device and method of operation are described. The memory device may include NAND memory. The memory device may configure a host device to maintain a host-side buffer for data backup. When the memory device determines an error associated with attempting to write data to a page of memory in a memory block, the memory device may indicate the error to the host device. The host device may, based on receiving the indication of the error, transmit to the memory device a backup copy of the data and other impacted data from the circular buffer. The memory device may configure the host-side buffer to have at least a particular size based one or more structural or operational aspects of the memory device.

A memory device is provided that includes a memory array including a first array, a first redundant array that is local to the first array, a second array, and a second redundant array that is local to the second array, a cache array including a first cache, a first redundant cache that is local to the first cache, a second cache and a second redundant cache that is local to the second cache, and circuits comprising logic to execute operations. The operations include, responsive to an identification of a defective column in the first array, performing a local defect write repair and responsive to an identification of another defective column in the first array and a determination that the first redundant array is fully utilized, performing a global defect write repair by transferring data into the second redundant array through the first cache and the second redundant cache.

A memory device is provided that includes a memory array including a first array, a first redundant array that is local to the first array, a second array, and a second redundant array that is local to the second array, a cache array including a first cache, a first redundant cache that is local to the first cache, a second cache and a second redundant cache that is local to the second cache, and circuits comprising logic to execute operations. The operations include, responsive to an identification of a defective column in the first array, performing a local defect write repair and responsive to an identification of another defective column in the first array and a determination that the first redundant array is fully utilized, performing a global defect write repair by transferring data into the second redundant array through the first cache and the second redundant cache.

A memory device and method of operation are described. The memory device may include NAND memory. The memory device may configure a host device to maintain a host-side buffer for data backup. When the memory device determines an error associated with attempting to write data to a page of memory in a memory block, the memory device may indicate the error to the host device. The host device may, based on receiving the indication of the error, transmit to the memory device a backup copy of the data and other impacted data from the circular buffer. The memory device may configure the host-side buffer to have at least a particular size based one or more structural or operational aspects of the memory device.

During a storage redundancy giveback from a first node to a second node following a storage redundancy takeover from the second node by the first node, the second node is initialized in part by receiving a node identification indicator from the second node. The node identification indicator is included in a node advertisement message sent by the second node during a giveback wait phase of the storage redundancy giveback. The node identification indicator includes an intra-cluster node connectivity identifier that is used by the first node to determine whether the second node is an intra-cluster takeover partner. In response to determining that the second node is an intra-cluster takeover partner, the first node completes the giveback of storage resources to the second node.

A memory device includes a non-volatile memory to store data, an execution trace buffer, and a media controller. The media controller receives data-modifying commands and adds the data-modifying commands to the execution trace buffer. The media controller executes the data-modifying commands to modify the data stored in the non-volatile memory and detects errors in the data stored in the non-volatile memory. The media controller repeats execution of data-modifying commands from the execution trace buffer in response to detecting an error.

The present invention relates to a power and video redundancy system for a display system of a smartboard. More particularly, the present invention relates to a power and video redundancy system applied to a smartboard display system which minimizes the user's inconvenience due to the failure or damage of components and enables the manager to repair or change the parts without the user being aware of the loss or damage.

A computer-implemented method for memory macro disablement in a cache memory includes identifying a defective portion of a memory macro of a cache memory bank. The method includes iteratively testing each line of the memory macro, the testing including attempting at least one write operation at each line of the memory macro. The method further includes determining that an error occurred during the testing. The method further includes, in response to determining the memory macro as being defective, disabling write operations for a portion of the cache memory bank that includes the memory macro by generating a logical mask that includes at least bits comprising a compartment bit, and read address bits.

A programmable display device for a production system that includes a storage device and a plurality of the programmable display devices. The storage device includes a plurality of individual memory areas that store data from the plurality of the programmable display devices individually and are associated with any one of the plurality of the programmable display devices. There is a backup processing unit that loads some or all data that the programmable display device itself retains into an individual memory area associated with the programmable display device itself among the plurality of individual memory areas and a state management unit that updates state management information retained in the storage device when the backup processing unit has performed data update within the individual memory area associated with the programmable display device itself. The state management information indicates that data retained by the plurality of individual memory areas have been updated.