A system and method for testing electronic circuit devices. The system has a central processing unit with a plurality of separate core processing units. The utility service program is initiated at the startup of the computer program which acts as an intermediary between user applications and the computer operating system. The utility service is responsive to an ATE execution engine to set an affinity for one or more processing cores for exclusive use for the ATE execution engine. The ATE execution engine communicates with the utility service to reserve one or more processing cores for execution of the program for testing electronic devices.

An embodiment of a system is disclosed, including an interface configured to communicate to a device under test (DUT). The DUT may include a plurality of processor cores. The system also includes a testing apparatus configured to concurrently measure a performance of a portion of each processor core to generate a first set of test values. Each test value of the first set may correspond to a given processor core of the plurality of processor cores. The testing apparatus may also be configured to analyze the first set of test values, and reject the DUT in response to a determination that at least one test value of the first set of test values exceeds a first threshold.

A method for providing a test response for testing a function of a master unit of a synchronous serial data bus, the method including a step of monitoring and a step of providing. In the step of monitoring, a command bit sequence on a command channel of the data bus is monitored in order to detect a predetermined command from the master unit. In the step of providing, the test response is provided on a response channel of the data bus in response to a detected predetermined command, a response bit sequence of the test response being provided by using a response rule predefined in a short-term memory.

Testing a data coherency algorithm of a multi-processor environment. The testing includes implementing a global time incremented every processor cycle and used for timestamping; implementing a transactional execution flag representing a processor core guaranteeing the atomicity and coherency of the currently executed instructions; implementing a transactional footprint, which keeps the address of each cache line that was used by the processor core; implementing a reference model, which operates on every cache line and keeps a set of timestamps for every cache line; implementing a core observed timestamp representing a global timestamp, which is the oldest construction date of data used before; implementing interface events; and reporting an error whenever a transaction end event is detected and any cache line is found in the transactional footprint with an expiration date that is older than or equal to the core observed time.

Testing a data coherency algorithm of a multi-processor environment. The testing includes implementing a global time incremented every processor cycle and used for timestamping; implementing a transactional execution flag representing a processor core guaranteeing the atomicity and coherency of the currently executed instructions; implementing a transactional footprint, which keeps the address of each cache line that was used by the processor core; implementing a reference model, which operates on every cache line and keeps a set of timestamps for every cache line; implementing a core observed timestamp representing a global timestamp, which is the oldest construction date of data used before; implementing interface events; and reporting an error whenever a transaction end event is detected and any cache line is found in the transactional footprint with an expiration date that is older than or equal to the core observed time.

In various embodiments, methods and systems for testing failover and recovery are provided. Systematic testing of a distributed system is performed, where the systematic testing probabilistically determines a processing order of events to effectuate system states for the plurality of state machines. An iteration of the systematic testing tests one the system states and includes sending a termination message to a state machine; receiving a termination acknowledgment message, the termination message causing the state machine to halt at the state and event of the state machine for the system state; and instantiating a recovery state machine. The recovery state machine is instantiated with a same state and same role as the halted state machine. Results of the systematic testing are verified against an expected outcome, the results being generated by running the distributed system with the instantiated recovery state machine for each iteration of the systematic testing.

A method for operating a multi-core processor system, wherein different of a program are each executed simultaneously by a different respective processor core of the multi-core processor system includes inserting a breakpoint in a first of the threads for interrupting the first processor core and instead executing an exception handling routine. At least one processor core to be additionally interrupted is determined with the exception handling routine on the basis of an association matrix, and an inter-processor interrupt (IPI) is sent to the at least one processor core by the exception handling routine in order to interrupt the at least one processor core.

Testing a data coherency algorithm of a multi-processor environment. The testing includes implementing a global time incremented every processor cycle and used for timestamping; implementing a transactional execution flag representing a processor core guaranteeing the atomicity and coherency of the currently executed instructions; implementing a transactional footprint, which keeps the address of each cache line that was used by the processor core; implementing a reference model, which operates on every cache line and keeps a set of timestamps for every cache line; implementing a core observed timestamp representing a global timestamp, which is the oldest construction date of data used before; implementing interface events; and reporting an error whenever a transaction end event is detected and any cache line is found in the transactional footprint with an expiration date that is older than or equal to the core observed time.

Systems and methods for automated system-level failure and recovery are described. In some embodiments, an Information Handling System (IHS) includes a processor and a memory, the memory having program instructions stored thereon that, upon execution by the processor, cause the IHS to execute a selected process configured to participate in an inter-process communication (IPC) with at least one other process, invoke an error handling process by simulating a fault in the IPC, and determine if the error handling process successfully handles the fault.

A method includes identifying a subset of components of a node that should be loaded during the next boot of the node, storing a list of the identified subset of components in a file outside of a basic input output system, and initiating boot of the node. The method further comprises the basic input output system accessing the file and controlling boot of the node to load only the identified subset of components of the node. Another method stores a plurality of such files, wherein each file is associated with maintenance of a target component of the node. After selecting one of the files, the basic input output system may access the selected file and control boot of the node to load only the subset of components that the selected file indicates should be loaded for purposes of a maintaining or testing the target component.