Techniques are disclosed for processor synchronization within a reconfigurable computing environment for processor array redundancy. Processing elements are configured within a reconfigurable fabric to implement two or more redundant processors, where the two or more redundant processors are enabled for coincident operation. An agent is loaded on each of the two or more redundant processors, where the agent performs a function requiring data validation. The agent is fired on each of the two or more redundant processors to commence coincident operation. The coincident operation can include a lockstep operation. An output data result from each of the two or more redundant processors is compared to enable a data validation result. The data validation result is propagated. The propagating the data validation result can be based on comparing valid output data or can be based on comparing invalid output data.

A method, apparatus and computer program product to be employed by a hardware component under validation, wherein the hardware component having a plurality of processing units each belonging to one of at least two types, such that one of the at least two types of processing units is less error-prone than a remainder of the at least two types. The method comprising: designating one of the processing units of the hardware component under validation that belongs to the less error-prone type as a manager processing unit; initiating execution of a tester program code for testing processing units, by processing units of the hardware component other than the manager processing unit; and, monitoring by the manager processing unit the status of the processing units during execution of the tester program code.

A network testing system includes one or more test devices each including a media-specific testing module and a processing device with a network interface, wherein the processing device is configured to test a network with the media-specific testing module; one or more servers configured to receive test results from the test of the network either directly from the one or more test devices or an intermediate data source communicatively coupled to the one or more test devices; and a validator module executed on the one or more servers configured to perform automated post-processing on the test results to compare the test results to a pre-defined Method of Procedure (MOP), to auto-correct one or more errors in the test results, and to provide a report based on the comparison.

A method of verifying processing logic of a graphics processing unit receives a test task including a predefined set of instructions for execution on the graphics processing unit, the predefined set of instructions being configured to perform a predetermined set of operations on the graphics processing unit when executed for predefined input data. In a test phase, the test task is processed by executing the predefined set of instructions for the predefined input data first and second times at the graphics processing unit so as to, respectively, generate first and second outputs. A fault signal is raised if the first and second outputs do not match.

Disclosed herein is a data processing system comprising a processing unit operable to process data to generate a sequence of outputs, wherein the processing unit is configurable, when generating a sequence of outputs, such that the data processing for generating an output in the sequence of outputs will be performed within a respective processing period for the output. A controller for the processing unit is configured to cause the processing unit, when generating a sequence of outputs, during a respective processing period for at least one output in the sequence of outputs, to also undergo one or more fault detection test(s) such that both processing of data for the output and fault detection testing is performed during the respective processing period for the output.

A computer-implemented method, computerized apparatus and computer program product for verification of atomic memory operations are disclosed. The method comprising: independently generating for each of a plurality of threads at least one instruction for performing an atomic memory operation of a predetermined type on an allocated shared memory location accessed by the plurality of threads; and, determining an evaluation function over arguments comprising values operated on or obtained in performing the atomic memory operation of the predetermined type on the allocated shared memory location by each of the plurality of threads; wherein the evaluation function is determined based on the atomic memory operation of the predetermined type such that a result thereof is not effected by an order in which each of the plurality of threads performs the atomic memory operation of the predetermined type on the allocated shared memory location.

Embodiments of the present invention relate to the field of computer technologies. The embodiments of the present invention provide a debugging method, including: stopping running, by a core A of a multi-core processor, and sending a running stop signal to other cores in a process of stopping running; after receiving a first stop termination instruction and resuming running, executing a debugging information collection function and stopping running after completing the execution of the debugging information collection function; after receiving a second stop termination instruction and resuming running, sending a running resumption instruction to the other cores; and knocking a pending breakpoint in a process of running an operation object of the preset event, so as to enter a debugging state. According to the technical solutions provided in the embodiments of the present invention, kernel mode code and user mode code can be debugged on a same debugging platform.

The present invention provides a smart overclocking method which comprises: providing a computer device with a multi-core CPU and building an overclocking database in a BIOS of the computer device; booting the computer device and logging in the BIOS and performing an overclocking function; acquiring overclocking numerical data in the overclocking database; performing adjustment of the frequency and the voltage of the multi-core CPU on the multi-core CPU with the overclocking numerical data; performing a heavy load pressure test on the multi-core CPU; reading in real time the working frequency, the working voltage, and the working temperature of the multi-core CPU and determining whether they have exceeded limits. Hence, after a user performs an overclocking function, a BIOS unit performs an overclocking test and determines the working frequency, the working voltage, and the working temperature, thereby achieving the efficacy that the BIOS unit can offer the optimized proposals for overclocking.

A computer-implemented method, computerized apparatus and computer program product for verification of atomic memory operations are disclosed. The method comprising: independently generating for each of a plurality of threads at least one instruction for performing an atomic memory operation of a predetermined type on an allocated shared memory location accessed by the plurality of threads; and, determining an evaluation function over arguments comprising values operated on or obtained in performing the atomic memory operation of the predetermined type on the allocated shared memory location by each of the plurality of threads; wherein the evaluation function is determined based on the atomic memory operation of the predetermined type such that a result thereof is not effected by an order in which each of the plurality of threads performs the atomic memory operation of the predetermined type on the allocated shared memory location.

A self-test controller includes a memory configured to store a test patterns, configuration registers, and a memory data component. The test patterns are encoded in the memory using various techniques in order to save storage space. By using the configuration parameters, the memory data component is configured to decode the test patterns and perform multiple built-in self-test on a multitude of test cores. The described techniques allow for built-in self-test to be performed dynamically while utilizing less space in the memory.