A method for applying an update includes sending a registration request to an update web service; receiving a delay parameter from the update service; checking for an update; comparing the update release date and the delay parameter with the current date to determine if the update should be installed; and installing the update when the current date is determined to be past the update release date plus the delay parameter.

An integrated circuit chip comprising: system circuitry comprising interconnect circuitry for transporting transactions; and monitoring circuitry configured to: monitor transactions from the interconnect circuitry comprising transactions between an entity and a specified region of the integrated circuit chip, the entity being associated with a set of one or more access rights for accessing the specified region of the integrated circuit chip; determine from the monitored transactions values of one or more parameters associated with the access to the specified region by the entity to identify whether the entity has breached its access rights; and perform a dedicated action indicative of a breach of the access rights in response to determining from the parameter values that the entity has breached its access rights.

A method, apparatus, article of manufacture, and system are provided for detecting hardware faults on a multi-core integrated circuit device by executing runtime software-based self-test code concurrently on multiple processor cores to generate a first set of self-test results from a first processor core and a second set of self-test results from a second processor core; performing mutual inter-core checking of the self-test results by using the first processor core to check the second set of self-test results from the second processor core while simultaneously using the second processor core to check the first set of self-test results from the first processor core; and then using the second processor core to immediately execute a recovery mechanism for the first processor core if comparison of the first set of self-test results against reference test results indicates there is a hardware failure at the first processor core.

Embodiments of the present invention relate to the field of computer technologies. The embodiments of the present invention provide a debugging method, including: starting, by a core A of a multi-core processor after completing execution of a preset event processing routine, to stop running, and sending a running stop signal to other cores in a process of stopping running; after receiving a first stop termination instruction and resuming running, executing a debugging information collection function to collect debugging information of the preset event, and stopping running after completing the execution of the debugging information collection function; and after receiving a second stop termination instruction and resuming running, sending a running resumption instruction to the other cores. By means of the technical solutions provided in the embodiments of the present invention, kernel mode code and user mode code can be masked on a same debugging platform.

The present invention provides a vehicle control device with which, even when an abnormality is detected in a core in a multi-core processor, it is possible to reduce the time needed until the core in which the abnormality is detected restarts and re-executes application software. The present invention is characterized by being provided with: a diagnostic means for carrying out a diagnostic process when starting a processor core, the diagnostic process including hardware diagnosis performed by hardware and software diagnosis performed using software after the hardware diagnosis; and a diagnostic process information change processing means for changing the method for executing the diagnostic process when all of the processor cores are started and when one of the processor cores is restarted.

A method for operating a control unit of a motor vehicle. A status inquiry is transmitted by a watchdog unit to a first monitoring unit, which is implemented on a first processor core of a multicore processor. A status response is ascertained by the first monitoring unit as a function of the status inquiry. A fault is ascertained by the watchdog unit as a function of the status response.

According to certain embodiments, a system includes one or more processors and one or more computer-readable non-transitory storage media comprising instructions that, when executed by the one or more processors, cause one or more components to perform operations including executing a software process of a secondary instance, the secondary instance running in parallel with a primary instance and associated with a plurality of cores including a bootstrap core, registering a non-maskable interrupt for the bootstrap core in the secondary instance, determining whether the secondary instance is in a fault state, wherein, if the secondary instance is in the fault state, halting the plurality of cores associated with the secondary instance, without impact to the primary instance, and recovering the bootstrap core by switching a context of the bootstrap core from the secondary instance to the primary instance via the non-maskable interrupt.

Aspects disclosed herein relate to periodic non-intrusive diagnosis of lockstep systems. An exemplary method includes comparing execution of a program on a first processing system of the plurality of processing systems and execution of the program on a second processing system of the plurality of processing systems using a first comparator circuit, comparing the execution of the program on the first processing system and the execution of the program on the second processing system using a second comparator circuit, and running a diagnosis program on the second comparator circuit while the comparing using the first comparator circuit is ongoing.

Apparatus and a method for processor core self-testing are disclosed. The apparatus comprises processor core circuitry to perform data processing operations by executing data processing instructions. Separate self-test control circuitry causes the processor core circuitry to temporarily switch from a first state of executing the data processing instructions to a second state of executing a self-test sequence of instructions, before returning to the first state of executing the data processing instructions without a reboot of the processor core circuitry being required. There is also self-test support circuitry, wherein the processor core circuitry is responsive to the self-test sequence of instructions to cause an export of at least one self-test data item via the self-test support circuitry to the self-test control circuitry.

Systems disclosed herein provide for efficient top-level compactors for systems on a chip (SoCs) with multiple identical cores. Embodiments of the systems provide for compactors with a time-skewed assignment configuration, compactors with a space-skewed assignment configuration, compactors with time/space-skewed assignment configuration, and compactors that can selectively switch between the time/space-skewed assignment configuration and a symmetric assignment configuration.