A controller may include: a ROM code register configured to generate and store a ROM code including a plurality of firmware images; and a ROM controller configured to change an operation setting of a ROM based on an operation firmware image of the plurality of firmware images, wherein each of the plurality of firmware images includes an image header including attribute information on a corresponding firmware image and image data, and wherein the operation firmware image includes, as its image header, an operation image header, which includes an operation mode field indicating whether the operation setting of the ROM is changed, and, as its image data, operation image data including information on the operation setting of the ROM.

According to an embodiment of the present invention, a computer implemented method and system for automated test and retesting in a virtual test environment, comprises: an input interface, comprising at least one processor, configured to receive one or more commands from a user, wherein the one or more commands comprise at least one test procedure and at least one system version parameter; a test and retest engine, comprising at least one processor, configured to execute the one or more commands on at least one system under test on a virtual environment based at least in part on the at least one system version parameter; and an output interface, comprising at least one processor, configured to receive results data responsive to execution of the one or more commands and further configured to display the results to the user.

Systems, apparatuses and methods may provide for receiving one or more debug communications and programming, via a bus, a set of debug registers with debug information corresponding to the one or more debug communications. Additionally, tunnel logic hardware may be instructed to transfer the debug information from the set of debug registers to one or more test access ports of an intelligent device such as a non-volatile memory storage unit having a microcontroller. In one example, if it is detected that debug permission has been granted during a boot process, a control status register may be unlocked. If, on the other hand, the debug permission is not detected during the boot process, the control status register may be locked. Accordingly, an enable bit of the control status register may be used to activate the tunnel logic hardware only if the control status register is unlocked.

An automated test equipment (ATE) system includes a plurality of test blades each coupled to a test blade connector and mounted on a circular track; a central reference clock (CRC) having an origin point at a center of the circle; and a clock/sync connector coupled to the CRC through a zero skew clock connection to one or more sync buses, wherein each instrument utilizes the CRC to coordinate its testing process with another instrument.

A memory test apparatus according to the present embodiment comprises a first storage medium temporarily retaining a test result of memory cells of a device under test in a plurality of divided portions based on data output from the device under test. A first processor reads the divided test result from the first storage medium to compress the test result. A second storage medium is provided to respectively correspond to a plurality of the devices under test and receives the compressed test result from the first processor and saves the compressed test result.

A method includes receiving tester configuration data, test pattern data, and tester operation data; configuring a circuit for performing a designated test evaluation; generating a stimulus waveform; converting the stimulus waveform to an analog stimulus signal; transferring the analog stimulus signal to a first terminal of a MTJ DUT at reception of a trigger timing signal; generating time traces based on the trigger timing signal; generating a response signal at a second terminal of the MTJ DUT and across a termination resistor as the analog stimulus signal is transferred through the MTJ DUT; converting the response signal to a digitized response signal indicating its voltage amplitude; and performing the designated test evaluation and analysis function in the configurable circuit based on voltage amplitudes and time values of the stimulus waveform, the digitized response signal, and the timing traces.

A test controller interfacing between a master computing device and slave computing devices includes a processor configured to launch a master application on the master computing device and a slave application to be tested on each respective slave computing device, with each slave application being the same as the master application. The processor is also configured to receive from the master computing device an input test command along with a test result based on execution of the input test command by the master application, and transmit the received input test command to each slave computing device. In addition, the processor is configured to receive a respective test result from each slave computing device based on execution of the received input test command, and compare each respective test result from the slave computing devices to the test result from the master computing device.

A method and computing system to recommend potential root causes of failure of an operation of a computer system is provided. An indication of a failed operation is received. A number of change orders (CO) that change one or more configuration items (CIs) that are associated with the operation from a baseline state to the current state of operation is determined. A root cause analysis (RCA) graph is displayed for a selected CO and has a plurality of CIs and connections therebetween in a first display area and a change order timeline in a second display area. Any of the number of CIs that were changed are highlighted. A potential cause listing in a third display area provides a list of highlighted CIs and a percentage indication by each highlighted CI that represents a calculated percentage that the CI is a potential cause of the failed operation.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for detecting system errors. One of the methods includes collecting an event log for the execution that identifies automated interactions with the application performed by an application testing agent; storing the event log in one or more content storage devices; storing event tracking data captured by a third party system during the automated interaction; comparing the first parameter types with the second parameter types to determine whether expected parameter types from the first parameter types are included in the second parameter types; comparing the corresponding first parameter values with the corresponding second parameter values for the same parameter type to determine whether the corresponding values are the same; and detecting a software error in one or more of the application, the third party system, or the event collection apparatus.

A stimulus/response controller within a magnetic electrical test apparatus is configured for generating and transmitting stimulus waveforms to a high-speed DAC for application to a MTJ DUT. The response signal from the MTJ DUT is applied to an ADC that digitizes and transfers the response signal to the stimulus/response controller. The stimulus/response controller has a configurable function circuit that is selectively configured for performing evaluation and analysis of the digitized stimulus and response signals. The configurable functions are structured for performing any evaluation and analysis function for determining the characteristics of the MTJ DUT(s). Examples of the evaluation and analysis operations include averaging the stimulus and/or response signals, determining the differential resistance, the degradation times, failure counts, or the bit error rate of the MTJ DUT(s). The evaluations and analysis of the MTJ DUT are then available for transfer to a tester controller within the magnetic electrical test apparatus.