An automated test equipment for testing one or more devices under test comprising a plurality of port processing units, comprising at least a respective buffer memory, and a respective high-speed-input-output, HSIO, interface for connecting with at least one of the devices under test. The port processing units are configured to receive data, store the received data in the respective buffer memory, and provide the data stored in the respective buffer memory to one or more of the connected devices under test via the respective HSIO interface for testing the one or more connected devices under test. A method and computer program for automated testing of one or more devices under test are also described.

An automated test equipment for testing a device under test comprises an on-chip-system-test controller. The on-chip system test controller comprises at least one debug interface or control interface configured to communicate with the device under test. The on-chip-system-test controller optionally comprises at least one high bandwidth interface configured to communicate with the device under test. The on-chip-system-test controller is configured to control a test of a device-under-test which is a system-on-a chip.

One or more embodiments provide a heterogeneous test equipment interfacing apparatus. The heterogeneous test equipment interfacing apparatus includes a plurality of data intermediate apparatuses connected to a plurality of environment test chambers; and at least one computer apparatus interoperating with the plurality of data intermediate apparatuses. Each of the plurality of data intermediate apparatuses is configured to convert an electric signal received from at least one environment test chamber interoperating with a corresponding data intermediate apparatus from among the plurality of environment test chambers into a data signal based on an SNMP protocol, output the data signal and, output a control signal for controlling the at least one environment test chamber interoperating with a corresponding data intermediate apparatus according to an operation control instruction received from the at least one computer apparatus.

A semiconductor device includes a debug port, a first access port, a second access port, a first processing unit, a second processing unit, and an embedded emulator unit. The first access port is coupled to the debug port. The second access port is coupled to the debug port. The first processing unit is coupled to the first access port. The second processing unit is coupled to the second access port. The embedded emulator unit is coupled to the debug port, the first processing unit and the second processing unit. The first processing unit generates a debug instruction to access the embedded emulator unit, so that the embedded emulator unit generates a debug signal. The debug signal is output to the second processing unit through the debug port and the second access port, so as to perform a debug operation on the second processing unit.

An electronic device, which can enter a debug mode, comprising: a plurality of buttons, wherein a layout of the buttons correspond to one of a first button layout and a second button layout; a processing circuit, configured to control the electronic device to enter a debug mode when at least two of the buttons are pressed to meet a predetermined button combination. The processing circuit controls the electronic device to perform a first test corresponding to the first button layout or to perform a second test corresponding to the second button layout to detect which one of the first button layout and the second button layout does the electronic device correspond to.

A configuration generating method for devices is applied to connecting ports and external devices connected to the connecting ports. The method includes the following steps: determining communication protocol types of the connecting ports respectively; generating a sequence list according to a plurality of device data, wherein each of the device data is corresponding to a communication protocol, the device data with ccTalk protocol are categorized in a first priority group, the device data with MDB protocol are categorized in a third sequence group, the device data other than those of the first priority group and the third priority group are categorized in a second priority group; and, testing the external devices sequentially and generating communication results according to the sequence list and the device data corresponding to the communication protocol types, and then generating a connecting ports configuration data of connecting ports according to the communication results.

Methods, articles, and systems of computer graphics processing system validation for processing of encrypted image content are disclosed herein.

A method for testing an interaction system response to different types of interaction devices is disclosed. A testing computer can execute various sets of interaction device logic during different test interaction. The testing computer can electronically communicate with an access device during test interaction through a conduit mobile device. As a result, the testing computer can electronically communicate with the access device even when the testing computer is remotely located.

In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.

A virtualizable automated test equipment architecture includes a circuit assembly. The circuit assembly includes a number of signal paths that extend between a front plane and a backplane. The signal paths can be continuous and isolated from other signal paths of the plurality of signal paths. The circuit assembly also includes an impedance disposed along a signal path of the plurality of signal paths. A plurality of software-configurable physical disconnects may be arranged within the circuit assembly to form a switching matrix. The plurality of signal paths can be associated with a plurality of software-configurable physical disconnects, which can be configured to open and close signal paths of the plurality of signal paths based on the predetermined test requirements. The circuit assembly also includes a plurality of external device connections, at least one of which may be configured to interface with a unit under test (UUT). The software configurable physical disconnects may be configurable at runtime. Because the system if virtualizable, multiplied UUTs may be tested simultaneously according to different requirements, and the testing may be executed on shared hardware in a manner transparent to the UUTs.