G06F11/2733

ERROR RATE MEASURING APPARATUS AND ERROR RATE MEASURING METHOD
20220398177 · 2022-12-15 ·

An error rate measuring apparatus detects a bit error of input data returned from a device under test with transmission of a test signal at an error detector, and includes a log recording unit that records log data of state transition of each lane by handshakes of a plurality of lanes in a predetermined communication standard with respect to the device under test in making the device under test transit to a state of LOOPBACK, and a display unit that displays the recorded log data of the state transition of each lane in a time-series order.

Wireless debugger and wireless debugging system
11526423 · 2022-12-13 · ·

Embodiments of the present disclosure provide a wireless debugger and a wireless debugging system. The wireless debugger includes: a processor, a wireless communication module, and a first peripheral interface; the processor is electrically connected to the wireless communication module and the first peripheral interface, respectively; the processor, is configured to receive debugging instructions through the wireless communication module, and the debugging instructions are used to instruct debugging/stop debugging a target board; the processor, is further configured to parse the debugging instructions and convert the parsed debugging instructions so that the debugging instructions are adapted to a protocol of the first peripheral interface; and the processor, is further configured to transmit the converted debugging instructions to the to-be-debugged target board through the first peripheral interface. Debugging control is convenient and reliable.

BASEBOARD MANAGEMENT CONTROLLER (BMC) TEST SYSTEM AND METHOD
20220390517 · 2022-12-08 · ·

An Information Handling System (IHS) includes multiple hardware devices, and a baseboard Management Controller (BMC) in communication with the plurality of hardware devices. The BMC includes a first processor configured to execute a custom BMC firmware stack, and a second processor including executable instructions for receiving a request to perform a test on the first processor in which the request is received through a secure communication session established with a remote IHS. The instructions further perform the acts of controlling the first processor to perform the test according to the request, the first processor generating test results associated with the test, and transmitting the test results to the remote IHS through the secure communication session.

Power storage adapter with power cable validation

A variable power bus (VPB) cable, such as a USB Type-C cable, is validated for actual current capacity with respect to a specified power rating for the cable. The power cable validation is performed when the cable is connected to a power storage adapter and a portable information handling system. The validation includes, prior to negotiating a power delivery contract for electrical power to be supplied to the information handling system from the VPB port via the VPB cable, applying a first voltage to the VPB cable to identify a first indication of a current capacity of the VPB cable; and when the first indication confirms that the current capacity of the VPB cable corresponds to a specified power rating for the VPB cable, enabling the power delivery contract to be negotiated according to the specified power rating, otherwise blocking the power delivery contract using the VPB cable.

DEVICE DETECTING SYSTEM

A device detecting system is provided. The device detecting system includes a bar code scanner, a plurality of device accommodating spaces, a screen, and a server. The server obtains bar code information via the bar code scanner and opens one of the device accommodating spaces based on the bar code information to accommodate an electronic device. The server performs a test procedure on the electronic device to generate a test result, and displays the test result and operation information corresponding to the test result on the screen.

RUNTIME IN-SYSTEM TESTING

During functional/normal operation of an integrated circuit including multiple independent processing elements (such as processors), a selected independent processing element is taken offline (e.g., by stopping functional operation of the independent processing element), and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation (e.g., standard application-specific operations). This enables the selected processing element to be robustly tested without stopping the regular operation of the integrated circuit.

Device maintenance apparatus, device maintenance method, and non-transitory computer readable storage medium

A device maintenance apparatus includes a test executor configured to cause a device to output an output signal based on a test pattern that changes the output signal output from the device with an elapse of time, and a change instructor configured to issue a change instruction for changing at least one of a progress of an output of the output signal based on the test pattern and an output value of the output signal to the test executor in accordance with an instruction input while the test executor causes the device to execute the output of the output signal.

Testing memory elements using an internal testing interface
11500017 · 2022-11-15 · ·

A semiconductor device comprises a plurality of memory elements, test control circuitry, and a testing interface. The test control circuitry is configure to determine that one or more clock signals associated with the memory elements have been stopped and generate a scan clock signal based on the determination that the one or more clock signals have been stopped. The test control circuitry is further configured to communicate the scan clock signal to the memory elements. The testing interface is configured to communicate test data from the memory elements. In one example, the test data is delimited with start and end marker elements. The semiconductor device is mounted to a circuit board and is communicatively coupled to communication pins of the circuit board.

Device diagnostic web system, device diagnostic method and program storage medium
11494279 · 2022-11-08 · ·

A device diagnostic web system that diagnoses a device locally connected to an information processing apparatus. In order to confirm whether or not access by the browser is to be permitted by connecting the device to the information processing apparatus via a local connection such as USB or Bluetooth, and executing a device diagnostic web application by a browser installed on this information processing apparatus, a confirmation screen for prompting a user to perform an operation of the information processing apparatus is displayed on the information processing apparatus, if the user permits the access, the device is communicatively connected to the browser to access the device and predetermined device information is acquired and diagnostic information is generated by using the acquired device information.

Leveraging low power states for fault testing of processing cores at runtime

In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.