In product testing, a script prioritization tool (102) is used to intelligently prioritize the execution sequence of test scripts. This tool creates a repository of test outputs from the executions of test scripts and analyzes the outputs to train and deploy a machine learning, ML, model that defines the priority of the scripts that may need to be executed and the scripts whose execution may be skipped without affecting the quality of testing. Scripts that are more likely to fail and/or are time consuming to execute are prioritized, while other scripts may be skipped. The ML model ranks the scripts based on the average execution time of the script, a count of the execution failures of the script, a count of the number of execution retries for the script, and the most recent failure time of the script. The scripts can be executed based on their rankings for efficiency and time-saving.

A trace-data-processing device for reconstructing an execution flow of a program performed by a source device under test or under observation, herein DUT, using at least one source-specific trace-data stream is disclosed. The trace-data-processing device comprises a trace-data-processing unit, which is configured to identify in the trace-data stream at least one instruction-synchronization message and branch messages. Moreover, the trace-data-processing device is configured to generate runtime-information data indicative of an at least partial reconstruction of the execution flow, using the identified trace messages, a pre-defined branch identifier allocated to each branch instruction address in the program that is associated with a direct branch instruction and pre-stored reconstruction information stored in a reconstruction memory.

A test and measurement instrument includes a system and/or method to generate a recommendation of a feature upgrade to the instrument. Such a method may include receiving a request by a user to perform an action on the instrument and performing the requested action by the instrument to generate first results. Then the instrument modifies an instrument parameter to one that is not presently available to the user, and performs the requested action again with the modified parameter to generate second results. After both results are generated, the instrument compares the first results to the second results and informs the user when the second results differ from the first results. Informing the user may include instructions for upgrading the instrument to include the modified parameter.

A virtualizable automated test equipment architecture includes a circuit assembly. The circuit assembly includes a number of signal paths that extend between a front plane and a backplane. The signal paths can be continuous and isolated from other signal paths of the plurality of signal paths. The circuit assembly also includes an impedance disposed along a signal path of the plurality of signal paths. A plurality of software-configurable physical disconnects may be arranged within the circuit assembly to form a switching matrix. The plurality of signal paths can be associated with a plurality of software-configurable physical disconnects, which can be configured to open and close signal paths of the plurality of signal paths based on the predetermined test requirements. The circuit assembly also includes a plurality of external device connections, at least one of which may be configured to interface with a unit under test (UUT). The software configurable physical disconnects may be configurable at runtime. Because the system if virtualizable, multiplied UUTs may be tested simultaneously according to different requirements, and the testing may be executed on shared hardware in a manner transparent to the UUTs.

Techniques for testing semiconductor devices include a semiconductor device having a plurality of components, a test bus, and a test data transfer unit. The test data transfer unit receives, from a host computer, configuration information for performing a test of the semiconductor device, reads, via a high-speed data transfer link, test data associated with the test from memory of the host computer using direct memory access, sends the test data to the plurality of components via the test bus, causes one or more operations to be performed on the semiconductor device to effect at least a portion of the test, and after the one or more operations have completed, retrieves test results of the at least a portion of the test from the test bus and stores, via the high-speed data transfer link, the test results in the memory of the host computer using direct memory access.

Methods, articles, and systems of computer graphics processing system validation for processing of encrypted image content are disclosed herein.

A compute node includes a network-connected device, and a baseboard management controller (BMC) that is connected to the network-connected device by a sideband interface. The network-connected device is configured to communicate with a network. The BMC is configured to configure the network-connected device, via the sideband interface, to engage in a debug session over the network with a remote debug device.

A GUI testing device may be configured to execute a testing state machine for interacting with a software application to generate an initial screen of a GUI. The GUI testing device may be configured to determine a current state in the testing state machine based upon a matching trigger target in the initial screen to a given state. The current state may include an operation, and the operation may associate with a trigger target to operate on. The trigger may include a source state, a destination state, and a trigger target. The operation may include a user input operation, and an operation trigger target. The GUI testing device may be configured to perform the operation on the matching trigger target in the initial screen to generate a next screen of the GUI, and advance from the current state to a next state based upon the trigger.

The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.

An automatic robot control system and methods relating thereto are described. These systems include components such as a touch screen panel (“TSP”) robot controller for controlling a TSP robot, a camera robot controller for controlling a camera robot and an audio robot controller for controlling an audio robot. The TSP robot operates inside a TSP testing subsystem, the camera robot operates inside a camera testing subsystem, and the audio robot operates inside an audio testing subsystem. Inside the audio testing subsystem, an audio signals measurement system, using a bi-directional coupling, controls the operation of the audio robot controller. In this control scheme, a test application controller is designed to control the different types of subsystem robots. Methods relating to TSP, camera, and audio robots, and their controllers, taken individually or in combination, for automatic testing of device functionalities are also described.