An electronic device, which can enter a debug mode, comprising: a plurality of buttons, wherein a layout of the buttons correspond to one of a first button layout and a second button layout; a processing circuit, configured to control the electronic device to enter a debug mode when at least two of the buttons are pressed to meet a predetermined button combination. The processing circuit controls the electronic device to perform a first test corresponding to the first button layout or to perform a second test corresponding to the second button layout to detect which one of the first button layout and the second button layout does the electronic device correspond to.

A component die validation built-in self-test (VBIST) engine is presented. In an aspect, a component die includes component circuitry for performing a component function, interface circuitry for communicating with another die, and a VBIST circuit. The VBIST circuit includes a traffic generator that generates test data streams, a tracker that receives and validates test data streams, and a configurable switching matrix for coupling the traffic generator to at least one of the component circuitry, the interface circuitry, or the tracker, and for coupling at least one of the component circuitry, the interface circuitry, or the traffic generator to the tracker. The VBIST circuit can send traffic to and from the component circuitry directly, or indirectly via the interface circuitry in loopback mode, and can be used for memory initialization and test.

An image processing apparatus includes a photographing device, an image processor and a fault diagnostic device. The photographing device outputs image data. The image processor includes an electronic circuit having recognition algorithms respectively for image recognition of a predetermined recognition target included in the image data. The fault diagnostic device determines that a fault occurs in the image processor, based on a condition that a first recognition result of recognizing test image data including a characteristic pattern also included in the recognition target in case of the image processor receiving the test image data is different from an expected value as a second recognition result of recognizing the test image data in case of one of the recognition algorithms receiving the test image data.

The present invention relates to a method of validating a memory device. The method includes validating a second memory device based on one or more first microcode instructions stored in a validated predetermined part of a first memory device to detect the operational status of the second memory device. Further, the method includes receiving one or more second microcode instructions upon validating the second memory device. Finally, validating the first memory device based on the one or more second microcode instructions stored in the second memory device to detect the operational status of the first memory device.

The present invention relates to a method of validating a memory device. The method includes validating a second memory device based on one or more first microcode instructions stored in a validated predetermined part of a first memory device to detect the operational status of the second memory device. Further, the method includes receiving one or more second microcode instructions upon validating the second memory device. Finally, validating the first memory device based on the one or more second microcode instructions stored in the second memory device to detect the operational status of the first memory device.

A device verification method, a UVM verification platform, an electronic apparatus, and a storage medium are provided. The method includes: determining a transaction class corresponding to a device under test, and instantiating a first interface in a callback function; sending input data to the device under test based on a bus protocol, and sequentially adding the input data to an array of the first interface according to addresses of the input data; instantiating a second interface in a monitor device, and sequentially adding output data to an array of the second interface according to addresses of the output data; and comparing the input data and the output data that have same addresses in the array of the first interface and the array of the second interface, and outputting a verification result of the device under test according to a comparison result.

A device verification method, a UVM verification platform, an electronic apparatus, and a storage medium are provided. The method includes: determining a transaction class corresponding to a device under test, and instantiating a first interface in a callback function; sending input data to the device under test based on a bus protocol, and sequentially adding the input data to an array of the first interface according to addresses of the input data; instantiating a second interface in a monitor device, and sequentially adding output data to an array of the second interface according to addresses of the output data; and comparing the input data and the output data that have same addresses in the array of the first interface and the array of the second interface, and outputting a verification result of the device under test according to a comparison result.

A semiconductor memory device includes a buffer die and a plurality of memory dies. Each of the memory dies includes a memory cell array, an error correction code (ECC) engine and a test circuit. The memory cell array includes a plurality of memory cell rows, each including a plurality of volatile memory cells. The test circuit, in a test mode, generates a test syndrome and an expected decoding status flag indicating error status of the test syndrome, receives test parity data generated by the ECC engine based on the test syndrome and a decoding status flag indicating error status of the test parity data, and determines whether the ECC engine has a defect based on comparison of the test syndrome and the test parity data and a comparison of the expected decoding status flag and the decoding status flag.

A semiconductor memory device includes a buffer die and a plurality of memory dies. Each of the memory dies includes a memory cell array, an error correction code (ECC) engine and a test circuit. The memory cell array includes a plurality of memory cell rows, each including a plurality of volatile memory cells. The test circuit, in a test mode, generates a test syndrome and an expected decoding status flag indicating error status of the test syndrome, receives test parity data generated by the ECC engine based on the test syndrome and a decoding status flag indicating error status of the test parity data, and determines whether the ECC engine has a defect based on comparison of the test syndrome and the test parity data and a comparison of the expected decoding status flag and the decoding status flag.

Aspects of the present disclosure relate to an apparatus comprising analogue circuitry comprising an entropy source, the entropy source being configured to provide a random output. The apparatus comprises first digital circuitry to receive the output of the entropy source and, based on said output, generate random numbers, and second digital circuitry to receive the output of the entropy source and, based on said output, generate random numbers, the second digital circuitry being a duplicate of the first digital circuitry. The apparatus comprises difference detection circuitry to determine a difference of operation between the first digital circuitry and the second digital circuitry. Each of the first digital circuitry and the second digital circuitry comprises entropy checking circuitry to check the entropy of the output of the entropy source.