Methods and apparatus relating to techniques for power management. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to generate a voltage/frequency curve for at least one of a core or a sub-core in a processor and manage an operating voltage level of the at least one of a core or a sub-core using the voltage/frequency curve. Other embodiments are also disclosed and claimed.

Methods and systems are described for obtaining a plurality of BER-specific correction values by comparing a first set of BER values obtained by sampling, at a sampling instant near the center of a signaling interval, a non-DFE corrected received signal with a second set of BER values obtained by sampling a DFE-corrected received signal at the sampling instant. A set of eye-scope BER measurements are obtained, each eye-scope BER measurement having a sampling offset relative to the sampling instant, a voltage offset value representing a voltage offset applied to alter a decision threshold, and an eye-scope BER value. A set of DFE-adjusted eye-scope BER measurements are generated by using BER-specific correction values to adjust the voltage offset values of the eye-scope BER measurements.

Methods and systems are provided for detecting artifacts in an electronic signal. In an embodiment, a method is provided comprising: connecting a first input of an electronic device to a first signal line of a signal processing device, such as an amplification device; connecting a second input of the electronic device to a second signal line of the signal processing device, the second signal line being downstream from the first signal line; establishing, based on an observed behavior of a first signal on the first signal line, an expected behavior of a second signal on the second signal line; and determining whether a difference exists between the expected behavior of the second signal and an observed behavior of the second signal. If a difference is detected, the expected behavior of a second signal and the observed behavior of the second signal may be recorded for later analysis.

A display apparatus includes: an operation input device configured to designate a data range of an observed value; an analysis condition setting device configured to determine an analysis range or an analysis parameter of the observed value, corresponding to the number of samples included in the data range; a computation device configured to analyze a waveform or a trend of the observed value on the basis of the analysis range or analysis parameter; and a display screen generation device configured to cause a display device to display a waveform or a straight line as a computation result of the computation device.

An improved approach is provided to provide fast access to waveform visualizations for electronic designs. Data reduction is performed on the waveform data, where the quantity of the waveform data is reduced in an intelligent manner, such that the reduced waveform data still retains sufficient data fidelity for accurate data analysis and waveform visualization. The reduced data can then be displayed in an accelerated manner. From the display of the reduced data, this allows the user to select only the specific one or more waveforms for which the user seeks viewing of the full waveform data.

Methods and apparatus relating to techniques for power management. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to generate a voltage/frequency curve for at least one of a core or a sub-core in a processor and manage an operating voltage level of the at least one of a core or a sub-core using the voltage/frequency curve. Other embodiments are also disclosed and claimed.

A diagnostic device includes an input unit that accepts input of an onomatopoeia to use in a sound sample search, a search unit that searches for a sound sample matching the input onomatopoeia, and a display that displays a search result from the search unit.

Various example implementations are directed to circuits and methods for debugging logic circuits utilizing a data bus for communication. According to an example implementation, an apparatus includes a logic circuit configured to communicate data over a data bus according to a communication protocol. The apparatus also includes a logic analyzer circuit coupled to the data bus. The logic analyzer circuit is configured to capture, in response to a control signal, samples of data signals communicated on the data bus. The logic analyzer circuit determines respective pairs of start and end positions of the data transactions in the captured samples. The logic analyzer circuit outputs the samples of the data signals and a set of metadata including the determined pairs of start and end positions of data transactions in the samples.

A processing system receives a time series of values of a first metric corresponding to computing system performance. A computation module calculates an autocorrelation function (ACF) based on the time series of values across a set of values of tau. The spacing between each consecutive pair of values in the set of values of tau increases as tau increases. A local maxima extraction module identifies local maxima of the calculated ACF. A period determination module determines a significant period based on spacing between the local maxima and selectively outputs the significant period as a periodicity profile. A baseline profile indicating normal behavior of the first metric is generated based on the periodicity profile. An anomaly identification module selectively identifies an anomaly in present values of the first metric in response to the present values deviating outside the baseline profile.

A computer-implemented mechanism is provided that monitors usage of one or more computing resources within a set of computing components relative to a received workload. The mechanism calculates a maximum workload for the set of computing components from the monitored use of the computing resources within the set of computing components and determines an available overhead between the calculated maximum workload for the set of computing components and a current workload being performed by the set of computing components. The mechanism selects one or more maintenance tasks for the set of computing components, the total workload of the selected maintenance tasks being less than the determined available overhead.