A system and method is disclosed for the combined analysis of transaction execution monitoring data and a topology model created from infrastructure monitoring data of computing systems involved in the execution of the monitored transactions. Monitored communication activities of transactions are analyzed to identify intermediate processing nodes between sender and receiver side and to enrich transaction monitoring data with data describing those intermediate processing nodes. The topology model may also be improved by the combined analysis, as functionality and services provided by elements of the topology model may be derived by the involvement of those elements in the execution of monitored transactions. The result of the combined analysis is used by an automated anomaly detection and causality estimation system. The combined analysis may also reveal entities of a monitored environment that are used by transaction executions but which are not monitored.

Systems and methods for generating and evaluating driving scenarios with varying difficulty levels is provided. The disclosed systems and methods may be used to develop a suite of regression tests that track the progress of an autonomous driving stack. A robustness trace of a temporal logic formula may be computed from an always-eventually fragment using a computation graph. The robustness trace may be approximated by a smoothly differentiable computation graph, which can be implemented in existing machine learning programming frameworks. The systems and methods provided herein may be useful in automatic test case generation for autonomous or semi-autonomous vehicles.

A system and method is disclosed for the combined analysis of transaction execution monitoring data and a topology model created from infrastructure monitoring data of computing systems involved in the execution of the monitored transactions. Monitored communication activities of transactions are analyzed to identify intermediate processing nodes between sender and receiver side and to enrich transaction monitoring data with data describing those intermediate processing nodes. The topology model may also be improved by the combined analysis, as functionality and services provided by elements of the topology model may be derived by the involvement of those elements in the execution of monitored transactions. The result of the combined analysis is used by an automated anomaly detection and causality estimation system. The combined analysis may also reveal entities of a monitored environment that are used by transaction executions but which are not monitored.

A resource prediction system for executing machine learning models and method are provided. The system includes non-transitory memory storing instructions and a processor configured to execute the instructions to obtain input data including a targeted objective and the constraints, select a deployable machine learning model having an evaluation score that meets a predetermined criterion from among candidate machine learning models, virtually execute the deployable machine learning model on each of candidate hardware platforms according to the constraints, generate an assessment report of the virtual performance metrics set of the deployable machine learning model executed on each of the candidate hardware platforms, and select the suggested hardware platform meeting the predetermined criterion from among the candidate hardware platforms.

In one embodiment, a processor comprises a fabric interconnect to couple a first cache agent to at least one of a memory controller or an input/output (I/O) controller; and a first cache agent comprising a cache controller coupled to a cache; and a trace and capture engine to periodically capture a snapshot of state information associated with the first cache agent; trace events to occur at the first cache agent in between captured snapshots; and send the captured snapshots and traced events via the fabric interconnect to the memory controller or I/O controller for storage at a system memory or storage device.

Transforming input data to enable execution of second executable code using trace data gathered during execution of first executable code. A trace of an execution of the first code is accessed. The trace stores data of an input that was consumed by first executable instructions of the first code. It is determined that the stored data of the input is usable as an input to second executable instructions of the second code. A difference in size/format of the stored data as used by the first instructions, compared to an input size/format expected by the second executable instructions, is identified. Based on the identified difference, a data transformation is determined that would enable the second instructions to consume the stored data. Execution of the second instructions is emulated using the stored data, including projecting the data transformation to enable the second instructions to consume the stored data.

A method for use in a computing device having a processor, the method comprising: executing a computer program on the processor; while the computer program is running, detecting whether any of a plurality of transition instructions of the computer program is executed, the detecting being performed by using resources that are external to the computer program; in response to detecting that a given one of the transition instructions is executed, detecting whether a current execution flow of the computer program matches a control flow graph for the computer program; and performing a countermeasure action based on one of a mismatch of the current execution flow of the computer program and the control flow graph or a current value of a memory location associated with the computer program; wherein the control flow graph for the computer program is generated by simulating an execution of the computer program.

A method for use in a computing device having a processor, the method comprising: executing a computer program on the processor; while the computer program is running, detecting whether any of a plurality of transition instructions of the computer program is executed, the detecting being performed by using resources that are external to the computer program; in response to detecting that a given one of the transition instructions is executed, detecting whether a current execution flow of the computer program matches a control flow graph for the computer program; and performing a countermeasure action based on one of a mismatch of the current execution flow of the computer program and the control flow graph or a current value of a memory location associated with the computer program; wherein the control flow graph for the computer program is generated by simulating an execution of the computer program.

In one example implementation, a computer-implemented method includes receiving, at a parallel processor complex, a task to be executed by the parallel processor complex. The parallel processor complex includes a trace processor and a plurality of task execution processors, each of the plurality of task execution processors having a plurality of trace buffers associated exclusively therewith. The method further includes creating, by the trace processor, a trace entry by allocating an element from a shared queue. The method further includes loading, by the trace processor, the trace entry into a common trace buffer. The method further includes loading, by the trace processor, the trace entry into one of the plurality of trace buffers based at least in part on an interface identifier and a queue pair index record. The interface identifier identifies the one of the plurality of task execution processors with which the trace entry is associated.

In one example implementation, a computer-implemented method includes receiving, at a parallel processor complex, a task to be executed by the parallel processor complex. The parallel processor complex includes a trace processor and a plurality of task execution processors, each of the plurality of task execution processors having a plurality of trace buffers associated exclusively therewith. The method further includes creating, by the trace processor, a trace entry by allocating an element from a shared queue. The method further includes loading, by the trace processor, the trace entry into a common trace buffer. The method further includes loading, by the trace processor, the trace entry into one of the plurality of trace buffers based at least in part on an interface identifier and a queue pair index record. The interface identifier identifies the one of the plurality of task execution processors with which the trace entry is associated.