Embodiments provide a thread classification method that represents stack traces in a compact form using classification signatures. Some embodiments can receive a stack trace that includes a sequence of stack frames. Some embodiments may generate, based on the sequence of stack frames, a trace signature that represents the set. Some embodiments may receive one or more subsequent stack traces. For each of the one or more subsequent stack traces, some embodiments may determine whether a subsequent trace signature has been generated to represent the sequence of stack frames included within the subsequent stack trace. If not, some embodiments may generate, based on the trace signature and other subsequent trace signatures that were generated based on the trace signature, the subsequent trace signature to represent the subsequent sequence of stack frames.

Systems, methods, and apparatuses relating to circuitry to precisely monitor memory store accesses are described. In one embodiment, a system includes a memory, a hardware processor core comprising a decoder to decode an instruction into a decoded instruction, an execution circuit to execute the decoded instruction to produce a resultant, a store buffer, and a retirement circuit to retire the instruction when a store request for the resultant from the execution circuit is queued into the store buffer for storage into the memory, and a performance monitoring circuit to mark the retired instruction for monitoring of post-retirement performance information between being queued in the store buffer and being stored in the memory, enable a store fence after the retired instruction to be inserted that causes previous store requests to complete within the memory, and on detection of completion of the store request for the instruction in the memory, store the post-retirement performance information in storage of the performance monitoring circuit.

For the purpose of reproducing a call stack accurately without restricting the range of application, a stack scanner extracts, from a stack area of a thread whose call stack is to be acquired in a memory space of an application process, possible return addresses that are addresses in a feasible region in the memory space each representing a command right after a function call command. A program analyzer analyzes a control flow representing a flow of control configured by a branch in a function that is called by the function call command right before the command represented by each of the possible return addresses and, when there is a route reaching a command currently being executed in the control flow, determines that the possible return address is a return address and, when there is not the route, determines that the possible return address is not a return address.

Various examples are provided related to cache miss classification. In one example, a method for classification of cache misses includes detecting a susceptible instruction of a program with frequent cache misses based upon performance monitoring units (PMU) based course grain sampling; collecting a memory access pattern of the susceptible instruction using breakpoint-based fine-grain sampling; and classifying a type of cache miss associated with the susceptible instruction. The type of cache miss can be classified as a capacity miss, a conflict miss, or a coherence miss using the memory access pattern of the susceptible instruction.

A method for controlling an automation system with visualization of program objects of a control program of the automation system, comprises determining a pointer address of the pointer element, determining a first address offset of the pointer address, identifying a program object that is spaced apart from the first memory location of the program state by the first address offset according to the arrangement structure of the program state as a first program object, the memory address of which in the first memory area corresponds to the pointer address of the pointer element, identifying the first program object with the pointer object referenced by the pointer element, determining a fully qualified designation of the identified pointer element, and displaying the fully qualified designation of the pointer object referenced by the pointer element on a display element connected to the controller. An automation system carries out the method.

Systems, methods, and software can be used to identify API use in a binary code. In some aspects, a method comprises: obtaining a base memory-write profile description for a binary code, wherein the description comprises: a base memory-write profile for each of a plurality of API calls in the binary code, wherein the base memory-write profile comprises a count of memory updates for each of a plurality of memory locations during an execution of a corresponding API call; receiving an execution request that invokes the binary code; generating an execution memory-write profile for the request, wherein the execution memory-write profile comprises a count of memory updates for each memory location during an execution of the request; determining, based on a comparison between the execution memory-write profile and the base memory-write profiles in the description, an API call corresponding to the request; and generating a notification indicating the determined API call.

Embodiments identify heap-hoarding stack traces to optimize memory efficiency. Some embodiments can determine a length of time when heap usage by processes exceeds a threshold. Some embodiments may then determine heap information of the processes for the length of time, where the heap information comprise heap usage information for each interval in the length of time. Next, some embodiments can determine thread information of the one or more processes for the length of time, wherein determining the thread information comprises determining classes of threads and wherein the thread information comprises, for each of the classes of threads, thread intensity information for each of the intervals. Some embodiments may then correlate the heap information with the thread information to identify code that correspond to the heap usage exceeding the threshold. Some embodiments may then initiate actions associated with the code.

The exemplary embodiments disclose a system and method, a computer program product, and a computer system for diagnosing technical issues. The exemplary embodiments may include collecting data relating to one or more technical issues, extracting one or more features from the collected data, determining one or more diagnoses based on the extracted one or more features and one or more models, and suggesting to a support agent one or more actions based on the one or more determined diagnoses.

Cache-based trace logging using tags in an upper cache level. A processor influxes a cache line into a first cache level from an upper second cache level. Influxing the cache line into the first cache level includes, based on the first cache level being a recording cache, the processor reading a tag that is (i) stored in the second cache level and (ii) associated with the cache line. Based on reading the tag, the processor determines whether a first value of the cache line within the second cache level has been previously captured by a trace. The processor performs one of (i) when the first value is determined to have been previously logged, following a logged value logic path when influxing the cache line; or (ii) when the first value is determined to have not been previously logged, following a non-logged value logic path when influxing the cache line.

A system for tracing transactions includes a system mapping engine configured to generate a multi-tier control point map based on linked transactions across one or more systems having different management software, wherein the linked transactions are identified from transaction records obtained from parsed source code and transaction data of the one or more source systems; and a tracing engine configured to trace the linked transactions across the one or more source systems based on the multi-tier control point map. The multi-tier control point map provides end-to-end transaction traceability via the linked transactions.