A semiconductor system includes one or more core chips including a plurality of memory banks; one or more replacement storage units; and a base chip suitable for: first detecting a memory bank having an access frequency that satisfies a first condition, second detecting whether an utilization rate of the first detected memory bank satisfies a second condition, and replacing the second detected memory bank with one among the replacement storage units.

Embodiments provide techniques for estimating seasonal indices for multiple periods. Some embodiments can receive a signal comprising a plurality of measures sampled over a span of time from an environment in which one or more processes are being executed. Some embodiments may then extract a seasonal effector and a de-seasonalized component from the signal. Next, some embodiments can apply one or more spline functions to the seasonal effector to generate a first model. Some embodiments may then apply a linear regression technique to the de-seasonalized component to generate a second model. Some embodiments may then initiate actions associated with the code. Some embodiments may then generate a forecast of the signal based on the first model and the second model. Next, some embodiments may initiate, based at least in part on the forecast, one or more actions associated with the environment.

A method for managing thread execution in a processing system is provided. The method includes setting a first watchpoint, and generating a first watchpoint trigger corresponding to the first watchpoint. In response to the first watchpoint trigger, execution of a first thread is controlled in accordance with a value stored in a first control register. Controlling the first thread may further include disabling execution of the first thread. The disabling execution of the first thread may occur within the first watchpoint region.

There is provided a method for debugging errors in a shared memory. The method comprises executing instrumented machine code of a plurality of processes to generate a recorded execution of each of the plurality of processes for deterministic replay of the recorded execution. The method further comprises logging accesses to the shared memory by each of the plurality of processes in a shared memory log for debugging errors in the shared memory by analysing the recorded executions and the shared memory log. The shared memory log is accessible by each of the plurality of processes.

An approach is provided for implementing memory profiling aggregation. A hardware aggregator provides memory profiling aggregation by controlling the execution of a plurality of hardware profilers that monitor memory performance in a system. For each hardware profiler of the plurality of hardware profilers, a hardware counter value is compared to a threshold value. When a threshold value is satisfied, execution of a respective hardware profiler of the plurality of hardware profilers is initiated to monitor memory performance. Multiple hardware profilers of the plurality of hardware profilers may execute concurrently and each generate a result counter value. The result counter values generated by each hardware profiler of the plurality of hardware profilers are aggregated to generate an aggregate result counter value. The aggregate result counter value is stored in memory that is accessible by a software processes for use in optimizing memory-management policy decisions.

There is provided a method for debugging errors in a shared memory. The method comprises executing instrumented machine code of a plurality of processes to generate a recorded execution of each of the plurality of processes for deterministic replay of the recorded execution. The method further comprises logging accesses to the shared memory by each of the plurality of processes in a shared memory log for debugging errors in the shared memory by analysing the recorded executions and the shared memory log. The shared memory log is accessible by each of the plurality of processes.

An offset address generator generates a plurality of offset addresses at an interval of a basic processing unit size on the basis of an access destination address from a calculating circuit, partitions an access destination memory region from the calculating circuit to set a plurality of verification address ranges. A determiner sequentially determines whether the plurality of set verification address ranges are matched with a monitoring target address. With this configuration, it is possible to simplify the configuration of a debug function in a processor.

Managing memory resources in a computing system may include receiving, from a computing system, data associated with memory transaction events originating from a process executing on the computing system; storing data related to memory transactions in multiple data structures according to metadata related to past memory transactions events; and altering memory storage or determining memory address translations based on the stored data.

The present disclosure relates to systems, methods, and computer-readable media for managing tracked memory usage data and performing various actions based on memory usage data tracked by a memory controller on a memory device. For example, systems described herein involve collecting and compiling data across one or more memory controllers to evaluate characteristics of the memory usage data to determine hotness metric(s) for segments of a memory resource. The systems described herein may perform a variety of segment actions based on the hotness metric(s). In addition, the systems described herein can compile the memory usage data according to one or more access granularities. This compiled data may further be shared with multiple accessing agents in accordance with access resolutions of the respective accessing agents.

The present disclosure provides an apparatus for analyzing trace information. The apparatus includes one or more storage devices that store a set of instructions, and one or more processors. The one or more processors are configured to execute the set of instructions to cause the apparatus to: obtain, from servers, processor instruction traces corresponding to workloads performed by the servers; generate address traces based on the processor instruction traces; and perform a workload analysis in accordance with the address traces to model resource demands of the workloads.