Patent classifications
G06F11/349
Monitoring system with multidrop backplane scheduler
Systems, methods, and devices for monitoring operation of industrial equipment are disclosed. In one embodiment, a monitoring system is provided that includes a passive backplane and one more functional circuits that can couple to the backplane. Each of the functional circuits that are coupled to the backplane can have access to all data that is delivered to the backplane. Therefore, resources (e.g., computing power, or other functionality) from each functional circuits can be shared by all active functional circuits that are coupled to the backplane. Because resources from each of the functional circuits can be shared, and because the functional circuits can be detachably coupled to the backplane, performance of the monitoring systems can be tailored to specific applications. For example, processing power can be increased by coupling additional processing circuits to the backplane.
DISTRIBUTION OF INTERCONNECT BANDWIDTH AMONG MASTER AGENTS
A method and apparatus for distributing interconnect bandwidth among master agents. The method includes allocating to each of the master agents a respective portion of the interconnect bandwidth within a time interval; monitoring the master agents to determine if any of the master agents has consumed its allocated portion of interconnect bandwidth within a current time interval; and if a master agent has consumed its allocated portion of interconnect bandwidth within the current time interval, delaying any new access requests from this master agent for a predetermined request delay time within the current time interval.
SYSTEM AND METHOD FOR HANDLING IN-BAND INTERRUPTS ON INACTIVE I3C CHANNELS
A multiplexor for an Improved Inter-Integrated Circuit (I3C) network includes a switch, a snooper, and an I3C slave module coupled to an I3C master interface. The switch selectably couples I3C busses to the I3C master interface. Each I3C bus incudes I3C slave interfaces. The selected I3C bus is the active bus, and the non-selected I3C busses are inactive buses. The snooper detects In-Band Interrupts (IBIs) from the I3C slave interfaces coupled to the inactive buses. When the snooper receives a first IBI on an inactive bus, the snooper provides an indication. The I3C slave module provides a second IBI to the I3C master interface in response to the indication.
Method for collecting performance data in a computer system
First information for a first event of a computer system is captured, including first event parameters. A first event key is generated, based on the first event parameters. The first information and first key are both stored as a first event in a storage structure, in which the first event key indexes the first event and the captured first information. When second information is captured for a second event, a second event key is generated based on second event parameters of the captured second event. If the second event key matches the first event key, then the first event stored in the event collection system is dynamically updated to store the second event information as part of the first event, to minimize additional storage space needed in the storage structure for the second event.
Microcontroller energy profiler
A method is disclosed to estimate energy consumed by a component in a microcontroller during operation including identifying “event” activities, where the energy consumed by the component may be determined by the number of events executed by the component, and “duration” activities, where the energy consumed may be determined by the duration of time required to execute of the activity, and determining the energy consumed by the component based on the number of events/duration of time and an energy coefficient which corresponds to the amount of energy consumed by the component to execute the activity, under given operating conditions. In an embodiment, data transfers at a bus interface may represent event activities. Apparatus to estimate the energy consumed is disclosed including bus monitors to receive signals representing data transfers at a bus interface and provide signals indicating the number of data transfers executed.
POWER MANAGEMENT INTEGRATED CIRCUIT (PMIC) MASTER/SLAVE FUNCTIONALITY
A power management integrated circuit (PMIC) capable of operating, in memory systems, as a master control in power management in some situations and operating as a slave control in power management in other situations. For example, when used in a memory system operating on a SATA bus, the PMIC assumes the master control by monitoring the bus signals for entering or existing a sleep mode or a power shutdown mode, communicating to the controller of the memory system to prepare for the respective mode, and when ready, adjusting power states for the mode changes. For example, when used in a memory system operating on a PCIe bus, the PMIC assumes the slave control during a normal mode and a sleep mode, but the master control when the memory system is in a power disable mode in which the controller of the memory system is powered off.
Improving efficiency of asynchronous input/output operations based on observed performance
Systems and methods for performing asynchronous input/output (I/O) operations. An example method comprises: initializing a list of sockets that are ready for performing I/O operations; traversing the list of sockets, wherein a traversal operation of the list includes, for each socket referenced by the list: performing I/O operations using the socket, updating a state flag associated with the socket to reflect a state of the socket; and responsive to detecting less than a threshold number of I/O operation errors during the traversal operation, updating the list of sockets based on updated state flags.
APPARATUS AND METHOD FOR DIAGNOSING FAULTS IN A FIELDBUS INTERFACE MODULE
A method and system for detecting faults in a communication interface is disclosed. The communication interface is connected to a field device and a device bus comprising generating periodic diagnostic pulse by a programing unit. The programming unit is communicatively connected to the controller and a controller interface and provides the diagnostic pulse to a multiplexer to periodically apply the diagnostic pulses from the programming unit to a first winding of a transformer. The programming unit provides the diagnostic pulse to the isolation unit. A sensing unit senses a voltage drop across a sense resistor, the sensing unit having an input connected to the sense resistor and an output connected to the programming unit. The sensing unit communicates a sense signal based on the comparison to the programming unit, and switches from a primary or a secondary module to the other based on the sense signal.
METHOD AND SYSTEM FOR GENERATING DIGITAL TWINS OF RESOURCE POOLS AND RESOURCE POOL DEVICES
A method for managing pool device resources, the method comprising: obtaining, by a digital twin service, a digital twin generation request, wherein the digital twin generation request specifies a pool device, identifying a plurality of PCI bus device being used by the pool device associated with the digital twin generation request, obtaining configuration information associated with the plurality of PCI bus devices, initiating a resource allocation using a virtual switch to access a peripheral component interconnect (PCI) bus device on a second pool device based on the configuration information and the plurality of PCI bus devices, performing performance calculations on the PCI bus device based on the resource allocation, and storing a result of the performance calculations.
Method and system for generating digital twins of resource pools and resource pool devices
A method for managing pool device resources, the method comprising: obtaining, by a digital twin service, a digital twin generation request, wherein the digital twin generation request specifies a pool device, identifying a plurality of PCI bus device being used by the pool device associated with the digital twin generation request, obtaining configuration information associated with the plurality of PCI bus devices, initiating a resource allocation using a virtual switch to access a peripheral component interconnect (PCI) bus device on a second pool device based on the configuration information and the plurality of PCI bus devices, performing performance calculations on the PCI bus device based on the resource allocation, and storing a result of the performance calculations.