A method for analyzing how a baseboard management controller (BMC) is monitoring a device in an analysis system platform performs an analysis of features of the device being monitored by the BMC. The method receives an IP address of a BMC input by a user, obtains source code corresponding to the IP address and determines application programming interface type corresponding to the source code. A function menu according to the application programming interface type is selected, the function menu comprising at least one item for analysis. The feature performance of the device being monitored is analyzed and recorded and results of the performance analysis are stored.

An integrated circuit (IC) includes a first circuit including a timer for receiving an adjustable clock signal. Responsive to leaving the non-operational power state to enter a power state in which the adjustable clock has a lower frequency than the reference clock, the first circuit adjusts the frequency of the adjustable clock to a frequency higher than the lower frequency, and then receives an elapsed time associated with the non-operational power state and starts the timer using an adjusted timer value.

The embodiments of the present disclosure relate to a device and method for inspecting process and an electronic control device. The device for inspecting process may include a converting controller configuring to be controlled for, when a preset operation is performed in a serial communication, converting into at least one process monitoring message by inputting a specific value into a dummy area included in at least one message corresponding to the preset operation, and an inspecting controller configuring to be controlled for inspecting a process based on the process monitoring message.

Data processing apparatus comprises a data access requesting node; data access circuitry to receive a data access request from the data access requesting node and to route the data access request for fulfilment by one or more data storage nodes selected from a group of two or more data storage nodes; and indication circuitry to provide a source indication to the data access requesting node, to indicate an attribute of the one or more data storage nodes which fulfilled the data access request; the data access requesting node being configured to vary its operation in response to the source indication.

The system, method, and computer program product described herein provide ways to modify a user interface when a performance of the user interface degrades due to lack of resources including presenting the user interface to a user that includes a first element that requires an allocation of a first amount of resources of a server to perform a function, determining that a performance of the user interface has degraded below a threshold amount, in response to determining that the performance has degraded, identifying a second element that requires an allocation of a second amount of resources of the server to perform the function where the second amount of resources is smaller than the first amount of resources, and replacing the first element with the second element to reduce the required amount of resources that are allocated by the server to the user interface.

A method for testing performance of a page control comprising: testing each of multiple evaluation dimensions for a page control, the multiple evaluation dimensions comprising at least one of an FPS (Frames Per Second) at the time of scrolling a page, an FPS at the time of opening a message, the number of times of adding a message, an FPS at the time of cutting an image, an FPS at the time of adding a message, and the number of times of rendering a page; determining a test result of each of the evaluation dimensions; determining operation performance of the page control according to the test result of each of the evaluation dimensions. Also disclosed is an apparatus for testing performance of a page control, and an electronic device. Operation performance of the page control can be tested in multiple aspects and the credibility of performance evaluation results is improved.

An apparatus includes a processor, a first interface configured to connect to a bus of the apparatus, a second interface configured to communicate over a packet network, and circuitry. The circuitry is configured to, in a first operational mode, exchange data between the processor and one or more remote devices over the packet network, via the second interface, and in a second operational mode, monitor the bus using the first interface, detect a predefined trigger event occurring on the bus and, in response to detecting the trigger event, log one or more transactions on the bus that are adjacent to the trigger event and generate one or more protocol-analysis packets comprising at least part of the logged transactions.

A bus data analysis method comprises the steps of receiving an input signal, decoding the input signal according to a protocol, thereby extracting a data signal from the input signal, and analyzing the data signal extracted from the input signal statistically, thereby generating a statistically analyzed data signal. Furthermore, a bus data analysis system is described.

For each database subsystem in a plurality of database subsystems running in a logical partition (LPAR), the systems and techniques include collecting data from buffer pools on a periodic interval, monitoring real storage availability on the LPAR, calculating an input/output (I/O) intensity score for each buffer pool for the periodic interval, ranking the buffer pools based on the I/O intensity score, calculating a cumulative I/O intensity score for each buffer pool across a cycle of multiple periodic intervals, ranking the buffer pools based on the cumulative I/O intensity score, and selecting a buffer pool candidate for page fixing. The buffer pool candidate for page fixing is a highest-ranked buffer pool from the plurality of buffer pools during the cycle based on the cumulative I/O intensity score that satisfies the real storage availability on the LPAR.

An apparatus in one embodiment includes at least one processing device, with the at least one processing device comprising a processor and a memory coupled to the processor. The at least one processing device is configured to monitor performance of respective ones of a plurality of paths for accessing a logical storage device, and responsive to detection of at least one specified condition in the monitored performance relating to at least a subset of the paths, to switch the logical storage device from utilization of a first access protocol to utilization of a second access protocol different than the first access protocol. For example, in some embodiments, the at least one processing device is configured to switch the logical storage device from a SCSI access protocol to an NVMe access protocol, and vice versa, responsive to congestion, errors or other detected performance conditions currently impacting one of the access protocols.