A method of identifying a cause of an anomalous feature measured from system circuitry on an integrated circuit (IC) chip, the IC chip comprising the system circuitry and monitoring circuitry for monitoring the system circuitry by measuring features of the system circuitry in each window of a series of windows, the method comprising: (i) from a set of windows prior to the anomalous window comprising the anomalous feature, identifying a candidate window set in which to search for the cause of the anomalous feature; (ii) for each of the measured features of the system circuitry: (a) calculating a first feature probability distribution of that measured feature for the candidate window set; (b) calculating a second feature probability distribution of that measured feature for window(s) not in the candidate window set; (c) comparing the first and second feature probability distributions; and (d) identifying that measured feature in the timeframe of the candidate window set as a cause of the anomalous feature if the first and second feature probability distributions differ by more than a threshold value; (iii) iterating steps (i) and (ii) for further candidate window sets from the set of windows prior to the anomalous window; and (iv) outputting a signal indicating those measured feature(s) of step (ii)(d) identified as a cause of the anomalous feature.

Provided is a method for regulating, via a hardware performance throttling block (PTB) of a memory module, the performance of a memory system in response to read and write requests from a processing system which hosts the memory system. The host system sends memory service requests to the memory system in the form of memory read requests and memory write requests. The host system may also send requests to throttle, that is, to limit the responses of the memory system in response to memory requests; the host system may also send to the memory system various parameters indicative of current memory usage. In response to the throttling request, the PTB of the memory module either stops any reception of memory requests, or limits (throttles) the number of memory requests (either read requests, write requests, or both) for a specified number of clock/command cycles. The PTB also determines when full, un-throttled performance may be resumed.

Embodiments include herein are directed towards a system and method for monitoring compliance patterns. Embodiments may include a re-timer device-under-test configured to transmit a truncated compliance pattern associated with a PCIe compliance mode. Embodiments may further include a BFM monitor configured to receive the truncated compliance pattern and to identify a communication signal associated with the truncated compliance pattern. The BFM monitor may be further configured to discard at least one unexpected symbol on at least one lane associated with the communication signal and to collect compliance patterns on all lanes of the communication signal. The BFM monitor may be further configured to align one or more lane FIFOs based upon skew and to enable one or more compliance pattern checkers.

A processing device includes: a first processor configured to execute a determination process; and a second processor configured to communicate with the first processor via an internal bus, wherein the determination process includes processes of determining that the abnormality occurs inside the processing device when first reference data transmitted to the second processor and first diagnostic data that is response data to the first reference data do not correspond to each other, and determining that the abnormality occurs in at least one of an external bus or an external device when the first reference data and the first diagnostic data correspond to each other and second reference data transmitted to the external device and second diagnostic data that is response data to the second reference data do not correspond to each other.

In some implementations, a system may monitor session data associated with a first module and a second module of a platform. The system may determine a rate of communication between the first module and the second module based on the session data. The system may determine, using an optimization model, a co-location score associated with the first module and the second module based on the rate of communication, wherein the co-location score indicates an impact of co-location of the first module and the second module. The system may determine that the co-location score satisfies a co-location score threshold associated with an improvement to an operation of the platform. The system may perform an action associated with co-locating the first module and the second module.

One method occurs at a test controller of a network test system implemented using at least one processor. The method includes receiving test configuration information for configuring a testing scenario comprising an emulated data center environment implemented using multiple network emulation platforms that are interconnected, wherein the test configuration information includes switching fabric topology information for defining the emulated data center environment; configuring, using the test configuration information, the emulated data center environment including sending a set of configuration instructions to each of the network emulation platforms, wherein each set of configuration instructions include resource allocation instructions for allocating ASIC switch resources of a respective network emulation platform to one or more emulated switches; and configuring, using the test configuration information, a test session for testing a system under test (SUT) using the emulated data center environment and a network visibility infrastructure.

In some implementations, a system may monitor session data associated with a first module and a second module of a platform. The system may determine a rate of communication between the first module and the second module based on the session data. The system may determine, using an optimization model, a co-location score associated with the first module and the second module based on the rate of communication, wherein the co-location score indicates an impact of co-location of the first module and the second module. The system may determine that the co-location score satisfies a co-location score threshold associated with an improvement to an operation of the platform. The system may perform an action associated with co-locating the first module and the second module.

One method occurs at a test controller of a network test system implemented using at least one processor. The method includes receiving test configuration information for configuring a testing scenario comprising an emulated data center environment implemented using multiple network emulation platforms that are interconnected, wherein the test configuration information includes switching fabric topology information for defining the emulated data center environment; configuring, using the test configuration information, the emulated data center environment including sending a set of configuration instructions to each of the network emulation platforms, wherein each set of configuration instructions include resource allocation instructions for allocating ASIC switch resources of a respective network emulation platform to one or more emulated switches; and configuring, using the test configuration information, a test session for testing a system under test (SUT) using the emulated data center environment and a network visibility infrastructure.

In one embodiment, an apparatus comprises: a plurality of intellectual property (IP) circuits, each of the plurality of IP circuits including a configuration register to store a dynamic current budget; and a power controller coupled to the plurality of IP circuits, the power controller including a dynamic current sharing control circuit to receive current throttling hint information regarding a workload to be executed on at least some of the plurality of IP circuits and generate the dynamic current budget for each of the plurality of IP circuits based at least in part thereon. Other embodiments are described and claimed.

A method and system for detecting faults in a communication interface is disclosed. The communication interface is connected to a field device and a device bus comprising generating periodic diagnostic pulse by a programing unit. The programming unit is communicatively connected to the controller and a controller interface and provides the diagnostic pulse to a multiplexer to periodically apply the diagnostic pulses from the programming unit to a first winding of a transformer. The programming unit provides the diagnostic pulse to the isolation unit. A sensing unit senses a voltage drop across a sense resistor, the sensing unit having an input connected to the sense resistor and an output connected to the programming unit. The sensing unit communicates a sense signal based on the comparison to the programming unit, and switches from a primary or a secondary module to the other based on the sense signal.