A virtual machine that includes a plurality of processes executes on a computer processor. A record-replay file, trace annotations, and an application program interface request are received into the computer processor. The trace annotations and application program interface request are translated into record-replay commands. The record-replay commands capture data from the record-replay file, and the captured data can be accessed via a programmatic interface.

A method is disclosed. The method including receiving at a telemetry service a plurality of transaction responses from a plurality of components distributed across a network, wherein the plurality of transaction responses is generated to process a request originating from a source component, wherein the request includes a request identifier, wherein the plurality of transaction responses includes a plurality of code path identifiers. The method including generating a fingerprint associated with the request by concatenating the plurality of code path identifiers, wherein each transaction response includes the request identifier and a corresponding code path identifier. The method including storing the fingerprint in a data storage.

This document describes debugging multiple instances of code by detecting a variance in thread patterns of threads of execution relative to the multiple instances of executing code. A first instance of the code is executed and a first thread pattern is identified indicative of a first plurality of threads of execution of the first instance of the code. A second instance of the code is executed, the second instance of the code beginning executing prior to the first instance of the code completing executing, and a second thread pattern is identified indicative of a second plurality of threads of execution of the second instance of the code. A comparative representation of the first thread pattern and the second thread pattern is generated relative to each other. A variance between the first thread pattern and the second thread pattern relative to the comparative representation is identified, the variance typically being indicative of a bug in the code.

Techniques and devices are described for embedding data in an address stream on an interconnect, such as a memory bus. Addresses in an address stream indicate at least part of a location in memory (e.g., a memory page and offset), whereas data embedded in the address stream can indicate when metadata or other information is available to lend context to the addresses in the address stream. The indication of data in the address stream can be communicated using, for example, a mailbox, a preamble message in a messaging protocol, a checksum, repetitive transmission, or combinations thereof. The indication of data can be recorded from the address stream and may later be used to interpret memory traces recorded during a test or can be used to communicate with a memory device or other recipient of the data during testing or regular operations.

An apparatus and method are provided to control assertion of a trigger signal to processing circuitry. The apparatus has evaluation circuitry to receive program instruction execution information indicative of a program instruction executed by the processing circuitry, which is arranged to perform an evaluation operation to determine with reference to evaluation information whether the program instruction execution information indicates presence of a trigger condition. Trigger signal generation circuitry is used to assert a trigger signal to the processing circuitry in dependence on whether the trigger condition is determined to be present. Further, filter circuitry is arranged to receive event information indicative of at least one event occurring within the processing circuitry, and is arranged to determine with reference to filter control information and that event information whether a qualifying condition is present. The filter circuitry is arranged, on determining that the qualifying condition is not present, to prevent the presence of the trigger condition being notified to the trigger signal generation circuitry. This allows the monitoring of particular program instruction execution behaviour to be qualified so that the processing circuitry is only notified if in addition a qualifying event is determined to be present.

Embodiments of the present disclosure present devices, methods, and computer readable medium for techniques for measuring operational performance metrics, and presenting these metrics through an application programming interface (API) for developers to access for optimizing their applications. Exemplary metrics can include central processing unit or graphics processing unit time, foreground/background time, networking bytes (per application), location activity, display average picture luminance, cellular networking condition, peak memory, number of logical writes, launch and resume time, frame rates, and hang time. Regional markers can also be used to measure specific metrics for in application tasks. The techniques provide multiple user interfaces to help developers recognize the important metrics to optimize the performance of their applications. The data can be normalized over various different devices having different battery size, screen size, and processing requirements. The user interfaces can provide an intelligent method for visualizing performance changes for significant changes in application versions.

A computer receives a log file, where the log file comprises records associated with the instructions in a source code. The computer loads, using a debugger, the log file and the source code. The computer receives a loading address from the log file. The computer updates a debugging data format (DWARF) with the one or more records of the log file, where the DWARF is accessed using the loading address and comprises one or more data structure entries. The computer identifies a calling address from the log file and identifies the one or more data structure entries associated with the calling address.

Example implementations include a method of receiving a host command identifier associated with a host command, determining a device command associated with the host command and a memory controller device, receiving a device command timestamp corresponding to a time of the determining the device command, and determining a debug record contemporaneously with the determining the device command, the debug record including the host command identifier, a device command identifier associated with the device command, and the device command timestamp. Example implementations also include a device operably coupled to a memory array, and with a memory controller device configured to receive a host command identifier associated with a host command, and configured to determine a device command associated with the host command and a memory controller device, and a debug record generator device operatively coupled to the memory controller device and configured to receive a device command timestamp corresponding to a time of the determined device command, and configured to determine a debug record contemporaneously with the determining the device command, the debug record including the host command identifier, a device command identifier associated with the device command, and the device command timestamp.

A system includes one or more processors in communication with a memory and configured to receive a task to probe a portion of the memory associated with a version of a binary file during execution of the binary file. The task includes a portion of object code and a hash identifier, both associated with the version of the binary file. A database mapping hash identifiers to debug information associated with installed binary files is accessed. Debug information for the version of the binary file associated with the hash identifier is retrieved. A probing application is built using the debug information and the portion of object code. Upon execution of the version of the binary file, the probing application places the object code into the portion of the memory.

Diffing a plurality of subject replayable traces against a plurality comparison replayable traces includes identifying first mappings among sections of consecutive instructions recorded in the subject traces, identifying distinct subject sections within the subject traces, identifying second mappings among sections of consecutive instructions recorded in the comparison traces, and identifying a plurality of distinct comparison sections within the comparison traces. Each distinct subject section is compared against distinct comparison section(s) to determine a comparison status of each distinct subject section, including whether each distinct subject section is equal to a corresponding distinct comparison section, or different than the distinct comparison sections. The comparison status of a distinct subject section with respect a corresponding distinct comparison section is applied to each comparison section to which the distinct comparison section is mapped in the second mappings, and to each subject section to which the subject section is mapped in the first mappings.