Systems and methods for secure transaction authorization are provided. An emulator is instantiated on a host device and configured to emulate an integrated circuit having a different instruction set than an integrated circuit of the host device, and a guest operating system executing on the emulated integrated circuit is configured to communicate with a host operating system of the host device through an emulated network interface of the emulator. Under control of one or more guest operating system processes executing on the emulated integrated circuit, a request is received over a first secure communication channel from an application executing on the host operating system to authorize a transaction. An authorization result is received from a remote system over a second secure communication channel, and a response is sent to the application over the first secure communication channel indicating the authorization result.

For generating an application program (15) from a plurality of application program modules (12), a computerized application platform (1) comprises an application configuration module (11) configured to receive from a user of a communication terminal instructions, for defining a selection of the application program modules (12), and to generate an application program (15) using the selected application program modules (12). The application platform (1) further comprises a plurality of device profiles (13) for different types of mobile communication devices. Each device profile (13) includes hardware characteristics of a different type of mobile communication device. Furthermore, a testing module (111) is configured to emulate the application program (15) for the different types of mobile communication devices using the device profiles (13) and to transmit to the user of the communication terminal test output data generated by emulating the application program (15) for at least one type of the mobile communication devices.

A microcomputer includes a CPU core, a memory which stores a program to be debugged and a debugging program, an event detection unit which detects establishment of an event, a debug interruption generation unit which transits a program to the debugging program when the event is established, and a debug interface control unit. The CPU core executes the debugging program, thereby informing an emulator of an event number of the established event through the debug interface control unit, and right thereafter restarting execution of the program to be debugged.

Technologies for debugging hardware errors discovered during hardware assisted software verification processes are provided. For example, in one embodiment, a concurrent emulation debug environment including a concurrent emulation system, an emulation trace module and a model state module is provided. The concurrent emulation system includes an emulator and an emulation control station configured to allow simultaneous emulation of multiple electronic designs. The model state module is configured to record the state of the electronic designs during emulation and the emulation trace module is configured to capture trace data associated with the emulation. A backup and capture module is also disclosed that is configured to store the recorded state and the captured trace data for use during a hardware debug process.

A hardware monitor arranged to assess performance of a hardware design for an integrated circuit to complete a task. The hardware monitor includes monitoring and counting logic configured to count a number of cycles between start and completion of the symbolic task in the hardware design; and property evaluation logic configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the hardware design in completing the symbolic task. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design meets a desired performance goal and/or to exhaustively identify a performance metric (e.g. best case and/or worst case performance) with respect to completion of the task.

A debugging system includes an embedded device and a terminal computer. The embedded device includes a memory unit, and the memory unit includes a first buffer, the embedded device is configured for executing at least one instruction to generate at least one real-time debugging information, and writing the real-time debugging information into the first buffer. The terminal computer is connected to an in-circuit emulator (ICE) via a first interface, and the ICE is connected to the embedded device via a second interface. The terminal computer uses polling to read the real-time debugging information stored in the first buffer via the ICE, and deletes the real-time debugging information stored in the first buffer afterwards.

This disclosure involves debugging code for resource-constrained intelligent devices contemporaneously with executing object code on the intelligent device. For example, object code is transmitted to a radio device. A program counter entry is provided from the radio device to a computer via a communication link contemporaneously with a pause in execution of the object code at the radio device. A correspondence between the program counter entry and a portion of assembly code, which was used to generate the object code, is identified and is used to generate a list of additional program counter entries for pausing the object code's execution. The list is provided from the computer to the radio device and is used to pause the object code's execution at the radio device. Log data is provided from the radio device to the computer for display after pausing the object code's execution at one of these program counter entries.

An arrangement for disabling a configuration of a first programmable hardware component, having the first programmable hardware component, a second programmable hardware component, and a switching element. The first programmable hardware component has a configuration interface for configuring a logic of the first programmable hardware component, a data interface for communication of the logic with the second programmable hardware component, a debugging interface for debugging and configuring the logic, and a configuration monitoring interface for signaling a configuration process of the logic. The switching element is designed and connected to the debugging interface such that access to the debugging interface during a configuration process of the logic can be disabled.

A hardware profiling mechanism implemented by performance monitoring hardware enables page level automatic binary translation. The hardware during runtime identifies a code page in memory containing potentially optimizable instructions. The hardware requests allocation of a new page in memory associated with the code page, where the new page contains a collection of counters and each of the counters corresponds to one of the instructions in the code page. When the hardware detects a branch instruction having a branch target within the code page, it increments one of the counters that has the same position in the new page as the branch target in the code page. The execution of the code page is repeated and the counters are incremented when branch targets fall within the code page. The hardware then provides the counter values in the new page to a binary translator for binary translation.

Technologies for debugging hardware errors discovered during hardware assisted software verification processes are provided. For example, in one embodiment, a concurrent emulation debug environment including a concurrent emulation system, an emulation trace module and a model state module is provided. The concurrent emulation system includes an emulator and an emulation control station configured to allow simultaneous emulation of multiple electronic designs. The model state module is configured to record the state of the electronic designs during emulation and the emulation trace module is configured to capture trace data associated with the emulation. A backup and capture module is also disclosed that is configured to store the recorded state and the captured trace data for use during a hardware debug process.