A method for developing and testing an application for a device with one or more sensors using a sensor emulation environment that may allow testing of the application in a programmatic manner. The sensor emulation environment may emulate actual physical sensors. The sensor emulation environment may receive sensor simulation data from multiple types of sources of sensor data. A sensor data engine may receive sensor simulation data from a selected data source via an API. The data engine may provide data values at times that represent operation of a sensor. The sensor emulation environment may further include a sensor interface component that emulates a hardware interface to the emulated sensor in a physical target device such that application components, such as a driver, may interact with the sensor emulation environment.

A crosstalk emulator for a cable, preferably a xDSL telecommunication cable, represented by several emulation paths each comprising a first segment (L1a/L4a) serially connected to a second segment (L1b/L4b) on a printed circuit board PCB. The first and second segments of a same emulation path form an angle, e.g. of about 90 degrees, at their junction point. All the emulation paths have a same length and preferably run in parallel over the PCB. As a result, each emulation path crosses only once (X21) any other emulation path at a cross-point. Furthermore, the area occupied by the crosstalk emulator on the PCB is reduced with respect to a matrix topology, whereby the present topology can easily be extended to large numbers of couplings, allowing design guidance for a passive coupling emulator with a large amount of coupling elements (CP) at the cross-points.

A debugging system includes an embedded device and a terminal computer. The embedded device includes a memory unit, and the memory unit includes a first buffer, the embedded device is configured for executing at least one instruction to generate at least one real-time debugging information, and writing the real-time debugging information into the first buffer. The terminal computer is connected to an in-circuit emulator (ICE) via a first interface, and the ICE is connected to the embedded device via a second interface. The terminal computer uses polling to read the real-time debugging information stored in the first buffer via the ICE, and deletes the real-time debugging information stored in the first buffer afterwards.

A formal verification tool is used to assess the performance of a hardware design for an integrated circuit to complete a set of tasks. The tool monitors one or more control signals and/or data signals of an instantiation of the hardware design to identify start and completion of a symbolic task by the instantiation of the hardware design, the symbolic task representing the set of tasks. A number of cycles between the start and the completion of the symbolic task is counted, and it is verified that one or more formal properties related to the counted number of cycles are true for the hardware design. An indication of whether or not each of the one or more formal properties was successfully verified is outputted, the indication providing an exhaustive assessment of the performance of the instantiation of the hardware design in completing the set of tasks.

For generating an application program (15) from a plurality of application program modules (12), a computerized application platform (1) comprises an application configuration module (11) configured to receive from a user of a communication terminal instructions, for defining a selection of the application program modules (12), and to generate an application program (15) using the selected application program modules (12). The application platform (1) further comprises a plurality of device profiles (13) for different types of mobile communication devices. Each device profile (13) includes hardware characteristics of a different type of mobile communication device. Furthermore, a testing module (111) is configured to emulate the application program (15) for the different types of mobile communication devices using the device profiles (13) and to transmit to the user of the communication terminal test output data generated by emulating the application program (15) for at least one type of the mobile communication devices.

A hardware profiling mechanism implemented by performance monitoring hardware enables page level automatic binary translation. The hardware during runtime identifies a code page in memory containing potentially optimizable instructions. The hardware requests allocation of a new page in memory associated with the code page, where the new page contains a collection of counters and each of the counters corresponds to one of the instructions in the code page. When the hardware detects a branch instruction having a branch target within the code page, it increments one of the counters that has the same position in the new page as the branch target in the code page. The execution of the code page is repeated and the counters are incremented when branch targets fall within the code page. The hardware then provides the counter values in the new page to a binary translator for binary translation.

A method for developing and testing an application for a device with one or more sensors using a sensor emulation environment that may allow testing of the application in a programmatic manner. The sensor emulation environment may emulate actual physical sensors. The sensor emulation environment may receive sensor simulation data from multiple types of sources of sensor data. A sensor data engine may receive sensor simulation data from a selected data source via an API. The data engine may provide data values at times that represent operation of a sensor. The sensor emulation environment may further include a sensor interface component that emulates a hardware interface to the emulated sensor in a physical target device such that application components, such as a driver, may interact with the sensor emulation environment.

An apparatus for, and method of, simulated virtual component testing, including a processor and a memory, the processor configured to receive a specification datum, receive an application datum, generate emulation parameters as a function of the specification datum, generate a testing framework as a function of the emulation parameters, determine an integration datum as a function of the testing framework and the application datum, output a compatibility datum as a function of the integration datum, and display a user interface.

Methods, apparatus, systems, and articles of manufacture are disclosed to debug a hardware accelerator such as a neural network accelerator for executing Artificial Intelligence computational workloads. An example apparatus includes a core with a core input and a core output to execute executable code based on a machine-learning model to generate a data output based on a data input, and debug circuitry coupled to the core. The debug circuitry is configured to detect a breakpoint associated with the machine-learning model, compile executable code based on at least one of the machine-learning model or the breakpoint. In response to the triggering of the breakpoint, the debug circuitry is to stop the execution of the executable code and output data such as the data input, data output and the breakpoint for debugging the hardware accelerator.

Methods, apparatus, systems, and articles of manufacture are disclosed to debug a hardware accelerator such as a neural network accelerator for executing Artificial Intelligence computational workloads. An example apparatus includes a core with a core input and a core output to execute executable code based on a machine-learning model to generate a data output based on a data input, and debug circuitry coupled to the core. The debug circuitry is configured to detect a breakpoint associated with the machine-learning model, compile executable code based on at least one of the machine-learning model or the breakpoint. In response to the triggering of the breakpoint, the debug circuitry is to stop the execution of the executable code and output data such as the data input, data output and the breakpoint for debugging the hardware accelerator.