Embodiments of the present disclosure provide a method, a system, and a computer readable storage medium for detecting deviations from targeted design performance in accelerator/emulator environment. In an embodiment, the method comprises loading target vales for a performance metric onto a hardware-accelerated simulator; setting breakpoints to pause the simulator at defined intervals; simulating, by the hardware-accelerated simulator, execution of a circuit design. The method further comprises during the simulating, using said breakpoints to pause the simulating at the defined intervals, and during each pause, comparing a measured value for the performance metric to the target value for the performance metric; and ending the simulation when a specified condition based on said comparing is met. In embodiments, when a difference between the measured value for the performance metric and the target value for the performance metric is within a preset tolerance, the pause is ended and the simulation continues.

A memory check method, a memory check device and a memory check system are disclosed. The method includes the following. A debug file is generated according to a source code, where the debug file carries symbol information related to a description message in the source code. Memory data generated by a memory storage device in execution of a firmware is received. The debug file is loaded to automatically analyze the memory data. In addition, an analysis result is presented by an application program interface, where the analysis result reflects a status of the firmware with assistance of the symbol information.

A method for debugging a logic system design including a target module to be debugged. The method includes receiving a first gate-level netlist associated with the logic system design and a second gate-level netlist associated with the target module that are generated based on a description of the logic system design, obtaining runtime information of an input signal of the target module by running the first gate-level netlist, and obtaining runtime information of the target module by running the second gate-level netlist based on the runtime information of the input signal of the target module.

A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

Collecting runtime virtual machine external state for an application running in an application runtime virtual machine, for use in emulation of the application. A method includes identifying application bytecode for which runtime virtual machine external state is to be collected. The method further includes executing machine code generated from the bytecode to generate the runtime virtual machine external state. The method further includes collecting the runtime virtual machine external state. The method further includes storing the runtime virtual machine external state for use in emulating the application.

A continuous integration framework for developing software for transaction processing and method for using the same are described. In one embodiment, the method comprises generating a trusted artifact with a forward immutable continuous integration (CI) implemented as a build pipeline, wherein the artifact comprises updated software comprising payment processing code with an EMV vector kernel for processing of EMV-based card present transactions; and in response to the software update, performing end-to-end testing of EMV card present transactions using code commits from one or more code repositories, wherein the end-to-end testing comprises executing the code commits that includes executing payment processing code for processing EMV-based card present transactions with an EMV vector kernel and one or more emulated EMV cards, and running tests against the executing code commits to validate behavior the payment processing code including the EMV vector kernel, wherein the tests comprise running one or more emulated EMV cards against the vector kernel as part of one or more emulated EMV-based card present transactions and monitoring communications related to the one or more emulated EMV-based card present transaction communications.

A hardware monitor arranged to assess performance of a hardware design for an integrated circuit to complete a task. The hardware monitor includes monitoring and counting logic configured to count a number of cycles between start and completion of the symbolic task in the hardware design; and property evaluation logic configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the hardware design in completing the symbolic task. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design meets a desired performance goal and/or to exhaustively identify a performance metric (e.g. best case and/or worst case performance) with respect to completion of the task.

The present application discloses an on-chip code breakpoint debugging method, an on-chip processor, and a chip breakpoint debugging system. The on-chip processor starts and executes an on-chip code, and an output function is set at a breakpoint position of the on-chip code. The on-chip processor obtains output information output by the output function, and stores the output information into an off-chip memory. In one embodiment, according to the output information, output by the output function and stored in the off-chip memory, the on-chip processor can obtain execution conditions of the breakpoints of the on-chip code in real time, achieve the purpose of debugging multiple breakpoints in the on-chip code concurrently, and improve debugging efficiency.

Program source code defined in a multi-threaded imperative programming language can be compiled into a circuit description for a synchronous digital circuit (“SDC”) that includes pipelines and queues. During compilation, data defining a debugging network for the SDC can be added to the circuit description. The circuit description can then be used to generate the SDC such as, for instance, on an FPGA. A CPU connected to the SDC can utilize the debugging network to query the pipelines for state information such as, for instance, data indicating that an input queue for a pipeline is empty, data indicating the state of an output queue, or data indicating if a wait condition for a pipeline has been satisfied. A profiling tool can execute on the CPU for use in debugging the SDC.

Systems and methods of the present disclosure are directed to a method. The method can include obtaining simplified scenario data associated with a simulated scenario. The method can include determining, using a machine-learned perception-prediction simulation model, a simulated perception-prediction output based at least in part on the simplified scenario data. The method can include evaluating a loss function comprising a perception loss term and a prediction loss term. The method can include adjusting one or more parameters of the machine-learned perception-prediction simulation model based at least in part on the loss function.