An apparatus, including: a deterministic monitored device; an interconnect to communicatively couple the monitored device to a support circuit; a super queue to queue transactions between the monitored device and the support circuit, the super queue including an operational segment and a shadow segment; a debug data structure; and a system management agent to monitor transactions in the operational segment, log corresponding transaction identifiers in the shadow segment, and write debug data to the debug data structure, wherein the debug data are at least partly based on the corresponding transaction identifiers.

A computer-implemented method for synthesizing a digital circuit is disclosed. The method includes receiving producer instructions defining a producer processing thread; generating a producer register-transfer level (RTL) description of the producer processing thread; receiving consumer instructions defining a consumer processing thread; generating a consumer RTL description of the consumer processing thread; and automatically inferring generation of streaming hardware RTL in response to receiving the producer and consumer instructions.

A computer-implemented method for synthesizing a digital circuit is disclosed. The method includes receiving producer instructions defining a producer processing thread; generating a producer register-transfer level (RTL) description of the producer processing thread; receiving consumer instructions defining a consumer processing thread; generating a consumer RTL description of the consumer processing thread; and automatically inferring generation of streaming hardware RTL in response to receiving the producer and consumer instructions.

Provided are systems, methods, and media for concurrency conflict testing for shared resources. An example method includes identifying shared resources that are to be accessed by an application. Generating a plurality of concurrency test scenarios based on the shared resources. Analyzing a plurality of concurrency test cases to detect which concurrency test cases include a reference to the shared resources. Executing a concurrency test scenario. Performing the following while or before the concurrency test scenario is executing, obtaining analyzed concurrency test cases associated with the concurrency test scenario which referenced the shared resources, obtaining application modules pertaining to the obtained concurrency test cases, generating concurrency application modules by adding breakpoints to the obtained application modules, executing the obtained concurrency test cases until all of the obtained concurrency test cases are latched at the breakpoints, and simultaneously resuming the execution of the obtained concurrency test cases.

In accordance with embodiments of the present disclosure, an information handling system may include a host system with information handling resources, a management controller configured to provide out-of-band management of the information handling system, and a debugging circuit. The debugging circuit may receive a plurality of serial data streams from the management controller and the plurality of information handling resources, and provide access to at least a subset of the plurality of serial data streams to a debugging information handling system via a wireless interface.

Diagnostic operations upon a target apparatus 2 having a target transaction master 8 which initiates memory transactions with one or more target transaction slaves 12, 14, 16 are provided by halting operation of the target transaction master 8 while permitting continued operation within the target apparatus 2 of at least some of the target transaction slaves 12, 14, 16. Opening state data representing an operating state of the target transaction master 8 is transferred to a model transaction master 32. Further operation of the target transaction master 8 is emulated using the model transaction master 32 using the opening state data. Diagnostic operations are performed upon the model transaction master 32. When the model transaction master 32 emulates initiation of a memory transaction with a memory address mapped to one of the target transaction slaves 12, 14, 16, this initiates the memory transaction to be performed with the target apparatus 2. Pages of stored values from the memory address space of the target apparatus 2 may be cached within the emulation.

A method and system for generating and managing virtual industrial devices in an industrial network is disclosed. The method includes capturing data packets associated with an ongoing industrial communication between an industrial application and an industrial device. The method further includes segregating the captured data packets into one or more requests and the one or more responses by analyzing information included in the data packets. The method also includes storing the one or more requests along with the one or more responses for the ongoing industrial communication in memory. The method includes dynamically generating a virtual industrial device emulating the industrial device based on the stored one or more requests and the stored one or more responses. The method includes establishing a communication session between the generated virtual industrial device and the industrial application for performing one or more test operations on the generated virtual industrial device.

Debugging a program in an apparatus using a lockstep method are more efficiently performed.

A semiconductor apparatus includes a first processor core, a second processor core, a first debug circuit, a second debug circuit, and an error control circuit capable of outputting an error signal for stopping execution of a program by the first processor core and the second processor core. The second debug circuit performs setting regarding debugging different from that of the first processor core with respect to the second processor core. Even if a first processing result of the first processor core and a second processing result of the second processor core do not coincide with each other, the error control circuit invalidates the output of the error signal when the first processor core executes the program and the second processor core stops execution of the program based on the setting regarding debugging.

Techniques for using emulation to disassociate verification from stimulus in functional test are described. In one approach, a computer stores first data representing an initial state of an application and second data representing the same initial state of a model application, wherein the model application models expected behavior of the application. The computer selects actions for the application to perform and causes both the application and the model application to perform the actions. The computer updates the first and second data to represent the state of both the application and the model application after performing the actions. The computer then compares the first and second data to determine whether both refer to the same state. In response to a determination that the first data and the second data do not refer to the same state, the computer stores data indicating a test failure.

A memory check method, a memory check device and a memory check system are disclosed. The method includes the following. A debug file is generated according to a source code, where the debug file carries symbol information related to a description message in the source code. Memory data generated by a memory storage device in execution of a firmware is received. The debug file is loaded to automatically analyze the memory data. In addition, an analysis result is presented by an application program interface, where the analysis result reflects a status of the firmware with assistance of the symbol information.