An adapter for connecting an embedded system to a control computer having a standard interface, in particular a network interface, a first subcircuit, and a second subcircuit, the first subcircuit being designed to communicate with the control computer via the standard interface by means of a standard protocol, preferably XCP. The first subcircuit is designed to convert a protocol functionality requested in the standard protocol via the standard interface, out of a set of supported protocol functionalities into the call for one or more elementary functions out of a defined overall set of elementary functions. The first subcircuit is connected to the second subcircuit via an internal interface, wherein the second subcircuit has a programmable computing module which is configured to provide at least one elementary function out of the overall set of elementary functions which can be called up via the internal interface by means of a call.

To access metadata when debugging a device, debug access port circuitry including a debug interface receives commands from a debugger, and a bus interface coupled to a bus enables the debugger to access a memory system of the device. The device operates on data granules having associated metadata items, and the bus interface enables communication of both the data granules and the metadata items over the bus. The debug access port circuitry has storage elements accessible via the commands issued from the debugger, such that the accesses performed within the memory system via the bus interface are controlled in dependence on the storage elements accessed by the commands. A metadata storage element stores metadata items, and the debug access port circuitry is responsive to a command from the debugger to perform a memory direct access to transfer metadata items between the metadata storage element and the memory system.

In some examples, device debugging connection control and maintenance may include receiving, from a debug tool, a connection request to connect to a device to be debugged. Based on the connection request, a primary socket connection may be implemented via a Universal Serial Bus (USB) channel to the device. Based on the connection request, a backup socket connection may be implemented via a Wi-Fi channel to the device. Based on the implementation of the primary socket connection and the backup socket connection, maintenance of a debugging session may be controlled during performance of a debugging operation.

The present application relates to a kernel debugging system and method. The kernel debugging system includes: a user interface module, the user interface module being configured to edit program codes and output an execution result of the program codes; a compilation module, the compilation module being configured to compile the program codes into object files; and a Kwasm engine, the Kwasm engine being directly installed in a system kernel of an operating system, and being configured to interpret and execute the object files in a kernel mode, so as to obtain the execution result of the program codes. On the basis of the kernel debugging system, a user can write program codes like writing a common application program, namely, the program codes can be run and executed in a system kernel without paying attention to details of the system kernel.

A real-time debugger implementation maintains and manages multiple debug contexts allowing developers to interact with real-time applications without “breaking” the system in which the debug application is executing. The debugger allows multiple debug contexts to exist and allows break points in real-time and non-real-time code portions of one or more applications executing on a debug enabled core of a processor. A debug monitor function may be implemented as a hardware logic module on the same integrated circuit as the processor. Higher priority interrupt service requests may be serviced while otherwise maintaining a context for the debug session (e.g., stopped at a developer defined breakpoint). Accordingly, the application developer executing the debugger may not have to be concerned with processing occurring on the processor that may be unrelated to the current debug session.

A computer system includes an operating system, a memory coupled to the operating system, and a processor (e.g., an anti-debug processor) coupled to the operating system. The operating system receives, from a debug process, a request to create an essential debug object for attachment to a target process. The anti-debug processor scans a kernel memory of the operating system for the essential debug object and verifies a presence of the essential debug object in the kernel memory, and scans the kernel memory to identify a process that has stored in the kernel memory the essential debug object. The anti-debug processor then halts the debug process, without using an internal interface or function of the operating system, thereby preventing the debug process from attaching to the target process.

The present disclosure discloses a debug unit, comprising: a write register configured to store kernel write data written by a kernel of a processor, wherein the processor is communicatively coupled to a debugger configured to read the kernel write data, wherein the kernel write data is associated with a kernel write flag bit to indicate data validity of the kernel write data; and a control unit including circuitry configured to control access to the write register by the kernel of the processor and the debugger based on data validity indicated by the kernel write flag bit. The present disclosure further discloses a corresponding processor including the debug unit, a corresponding debugger communicatively coupled to the processor, and a corresponding debug system including the processor coupled to the debugger.

Provided are a method and an apparatus for debugging, and a system on chip. The method for debugging includes: a component to be debugged receives a debugging instruction from a controller, and the component to be debugged performs debugging operation according to the debugging instruction and configuration of a state machine inside the component to be debugged. Then an SW level debugging operation of component on system on chip can be achieved, which improves the debugging efficiency of these components with large amounts of data flow on system on chip.

An exemplary method is disclosed that facilitate the on-demand creation of an exemplary instrumented network device in a cloud infrastructure, remote server, evaluation platform, or customized testing server and to form a stack between the instrumented network device as a debug network device and a target network device. The control plane of the target network device then switches over, via a switchover operation, to the control plane of the debug network device, while the data-plane of the target network device continues to operate. Once switched over, the instrumentation (e.g., hardware or software) of the control plane or debug network device facilitates the debug, optimization, profile, and/or recovery of the physical network device, even in a live network.

A method and apparatus for masking errors in a DRAM write are disclosed to perform a partial write request with an SSD controller. In embodiments, write data from a host is provided to the controller that is not aligned to the DRAM data. The controller issues a read command from the LBA of a data storage device, and a corresponding write command to write the data received from the host, prior to receipt of the read data, to perform a partial write. The read data is error corrected, and in the event an error is found in the read data, bytes containing an error are masked. The read data, including masked read data, and write data are merged to form partial write data, and written to the DRAM. In certain embodiments, the partial write data may be provided to a logic analyzer to assess the masked read data for debug analysis.