The present disclosure provides a multi-core processor. The multi-core processor comprises a plurality of cores and a debug circuit, the debug circuit comprising debug circuits in the same number as that of the cores, transmission controllers in the same number as that of the cores, and a master control circuit, each of the debug circuits being connected to one core and one transmission controller, respectively, and all transmission controllers being connected to the master control circuit. Each of the debug circuits is configured to generate a debug event signal and respond to the generated debug event signal or received debug event signals generated by other debug circuits. Each of the transmission controllers is configured to respectively control transmission of the debug event signal between the respectively connected debug circuit and the master control circuit. The master control circuit is configured to forward debug event signals among different transmission controllers. The present disclosure can realize rapid configuration and control of debug event signal transmission, and at the same time lower power consumption of a debug circuit.

A method includes receiving, by a storage device and from a host device, a set of protocol parameters initialized by the host device. The set of protocol parameters are used to facilitate data transfer between the host device and the storage device. The method also includes determining that a threshold value associated with the data transfer between the host device and the storage device has been satisfied. The method further includes, in response to determining that the threshold value has been satisfied, sending, by the storage device and to the host device, the set of protocol parameters that were received from the host device.

Embodiments of the present disclosure provide a wireless debugger and a wireless debugging system. The wireless debugger includes: a processor, a wireless communication module, and a first peripheral interface; the processor is electrically connected to the wireless communication module and the first peripheral interface, respectively; the processor, is configured to receive debugging instructions through the wireless communication module, and the debugging instructions are used to instruct debugging/stop debugging a target board; the processor, is further configured to parse the debugging instructions and convert the parsed debugging instructions so that the debugging instructions are adapted to a protocol of the first peripheral interface; and the processor, is further configured to transmit the converted debugging instructions to the to-be-debugged target board through the first peripheral interface. Debugging control is convenient and reliable.

Example implementations include a method of receiving a host command identifier associated with a host command, determining a device command associated with the host command and a memory controller device, receiving a device command timestamp corresponding to a time of the determining the device command, and determining a debug record contemporaneously with the determining the device command, the debug record including the host command identifier, a device command identifier associated with the device command, and the device command timestamp. Example implementations also include a device operably coupled to a memory array, and with a memory controller device configured to receive a host command identifier associated with a host command, and configured to determine a device command associated with the host command and a memory controller device, and a debug record generator device operatively coupled to the memory controller device and configured to receive a device command timestamp corresponding to a time of the determined device command, and configured to determine a debug record contemporaneously with the determining the device command, the debug record including the host command identifier, a device command identifier associated with the device command, and the device command timestamp.

An integrated circuit includes: a debugger; and an interface coupled to the debugger. The interface has: arbitration logic coupled to the debugger; a power processor coupled to the arbitration logic; and a power management network coupled to the power processor. The integrated circuit also includes subsystems coupled to the interface. The debugger is configured to perform debugging operations of the subsystems via the interface.

Present implementations include an electronic device with a system processor (SP) region connectable to an SP, a primary device region connectable to a first electronic device, and a secondary device region disposed between the SP device region and the primary device region, and connectable to a second electronic device. Present implementations further include a debugger region including a debugger unit and disposed adjacent to the primary device region and the secondary device region. Present implementations also include obtaining a debug selection including a debugger selection and a system processor (SP) selection, entering a first debug mode in accordance with a determination that the debugger selection satisfies a debugger criterion and the SP selection satisfies an SP criterion, and entering a second debug mode in accordance with a determination that the debugger selection satisfies the debugger criterion and the SP selection does not satisfy the SP criterion, and entering a third debug mode in accordance with a determination that the debugger selection does not satisfy the debugger criterion.

A version management method includes the following steps: selecting a master branch; receiving bug information, wherein the bug information includes the bug state; and setting the bug state to a working state after receiving a confirmation assignment message corresponding to the bug information; in response to setting the bug state to the working state, generating a branch corresponding to the bug information based on the master branch, and merging modified code of the branch to a candidate branch; and in response to the release time arriving, merging the candidate branch to the master branch, and setting the bug state to a verification state.

In one embodiment, an apparatus includes: a first trace source to generate a plurality of first trace messages and a first local platform description identifier to identify the first trace source; a second trace source to generate a plurality of second trace messages and a second local platform description identifier to identify the second trace source; and a trace aggregator coupled to the first and the second trace sources, the trace aggregator to generate a global platform description identifier for the apparatus and output a trace stream including the global platform destination identifier, the first and second local platform description identifiers, the plurality of first trace messages and the plurality of second trace messages. Other embodiments are described and claimed.

Embodiments of the present disclosure provide a splicing screen debugging method, a splicing screen and a splicing wall. The splicing screen debugging method includes: receiving, by the currently-debugged splicing screen, at least two debugging commands sent by the debugging equipment in a wireless broadcast way, each of the at least two debugging commands being adapted to debug one splicing screen of the at least two splicing screens; selecting, by the currently-debugged splicing screen, a target debugging command from the at least two debugging commands; reading, by the currently-debugged splicing screen, location identification information in the target debugging command; reading, by the currently-debugged splicing screen, debugging parameters in the target debugging command in response to the location identification information matching local location information pre-stored in the currently debugging splicing screen; and debugging the currently-debugged splicing screen according to the debugging parameters.

Systems and methods for secure booting of secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in a PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in a non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD to the configuration engine. The secure PLD is configured to retrieve a pre-authentication status associated with the configuration image from the NVM, determine or verify the retrieved pre-authentication status associated with the configuration image includes a valid status, and boot the PLD fabric of the secure PLD using the configuration image.