Providing debugging support for a carried thread are disclosed. A debug agent converts between identifiers of carried threads and carrier threads. Further, a debug agent transfers debug configurations amongst multiple carrier threads associated with a same carried thread. With respect to debug configuration transfers, an agent receives, from a debugger, a command to set an active debug configuration for a carrier thread on which a carried thread is mounted. Responsive to determining that the carried thread is unmounted, the agent stores the active debug configuration for the carrier thread as a recorded debug configuration associated with the carried thread. The agent transmits a command to reset the active debug configuration on the carrier thread. Responsive to determining that the carried thread is mounted on a carrier thread, the agent retrieves the recorded debug configuration. The agent restores the recorded debug configuration as an active debug configuration on the current carrier thread.

Providing debugging support for a carried thread are disclosed. A debug agent converts between identifiers of carried threads and carrier threads. Further, a debug agent transfers debug configurations amongst multiple carrier threads associated with a same carried thread. With respect to identifier conversion, an agent receives, from a debuggee, a notification that an event occurred in association with a carrier thread. The agent determines that a carried thread is mounted on the carrier thread. The agent transmits, to the debugger, a notification that the event occurred in association with the carried thread.

A computer-implemented method for debugging an executable control flow graph that specifies control flow among a plurality of functional modules, with the control flow being represented as transitions among the plurality of functional modules, the computer-implemented method including: specifying a position in the executable control flow graph at which execution of the executable control flow graph is to be interrupted; wherein the specified position represents a transition to a given functional module, a transition to a state in which contents of the given functional module are executed or a transition from the given functional module; starting execution of the executable control flow graph in an execution environment; and at a point of execution representing the specified position, interrupting execution of the executable control flow graph; and providing data representing one or more attributes of the execution environment in which the given functional module is being executed.

An apparatus comprises processing circuitry 14 to perform data processing in response to instructions, the processing circuitry supporting speculative processing of read operations for reading data from a memory system 20, 22; and control circuitry 12, 14, 20 to identify whether a sequence of instructions to be processed by the processing circuitry includes a speculative side-channel hint instruction indicative of whether there is a risk of information leakage if at least one subsequent read operation is processed speculatively, and to determine whether to trigger a speculative side-channel mitigation measure depending on whether the instructions include the speculative side-channel hint instruction. This can help to reduce the performance impact of measures taken to protect against speculative side-channel attacks.

A real-time debugger implementation maintains and manages multiple debug contexts allowing developers to interact with real-time applications without breaking the system in which the debug application is executing. The debugger allows multiple debug contexts to exist and allows break points in real-time and non-real-time code portions of one or more applications executing on a debug enabled core of a processor. A debug monitor function may be implemented as a hardware logic module on the same integrated circuit as the processor. Higher priority interrupt service requests may be serviced while otherwise maintaining a context for the debug session (e.g., stopped at a developer defined breakpoint). Accordingly, the application developer executing the debugger may not have to be concerned with processing occurring on the processor that may be unrelated to the current debug session.

A real-time debugger implementation maintains and manages multiple debug contexts allowing developers to interact with real-time applications without breaking the system in which the debug application is executing. The debugger allows multiple debug contexts to exist and allows break points in real-time and non-real-time code portions of one or more applications executing on a debug enabled core of a processor. A debug monitor function may be implemented as a hardware logic module on the same integrated circuit as the processor. Higher priority interrupt service requests may be serviced while otherwise maintaining a context for the debug session (e.g., stopped at a developer defined breakpoint). Accordingly, the application developer executing the debugger may not have to be concerned with processing occurring on the processor that may be unrelated to the current debug session.

A real-time debugger implementation maintains and manages multiple debug contexts allowing developers to interact with real-time applications without breaking the system in which the debug application is executing. The debugger allows multiple debug contexts to exist and allows break points in real-time and non-real-time code portions of one or more applications executing on a debug enabled core of a processor. A debug monitor function may be implemented as a hardware logic module on the same integrated circuit as the processor. Higher priority interrupt service requests may be serviced while otherwise maintaining a context for the debug session (e.g., stopped at a developer defined breakpoint). Accordingly, the application developer executing the debugger may not have to be concerned with processing occurring on the processor that may be unrelated to the current debug session.

The current embodiments relate to systems and methods for providing a virtual sandbox. In one embodiment, an electronic request is received at a centralized virtual sandbox hosting service. The electronic request requests a virtual sandbox session. In response to the received request, a particular project, a particular platform, and/or a particular environment is determined. Based upon the particular project, the particular platform, and/or the particular environment a particular codebase from a set of codebases stored at a code store is selected. At the centralized virtual sandbox hosting service, a virtual sandbox is generated, the virtual sandbox provides an integrated development environment for the particular codebase. A virtual sandbox view is then provided at the remote client to enable a user of the remote client computer to see and perform interactions with the integrated development environment at the centralized virtual sandbox hosting service, via the remote client computer.

Apparatus and methods are disclosed for controlling execution of register access instructions in a block-based processor architecture using a hardware structure that indicates a relative ordering of register access instruction in an instruction block. In one example of the disclosed technology, a method of operating a processor includes selecting a register access instruction of the plurality of instructions to execute based at least in part on dependencies encoded within a previous block of instructions and on stored data indicating which of the register write instructions have executed for the previous block, and executing the selected instruction. In some examples, one or more of a write mask, a read mask, a register write vector register, or a counter are used to determine register read/write dependences. Based on the encoded dependencies and the masked write vector, the next instruction block can issue when its register dependencies are available.

An apparatus and method are provided for accessing metadata when debugging a device. In particular, debug access port circuitry is provided that comprises a debug interface to receive commands from a debugger, and a bus interface to couple to a bus to enable the debugger to access a memory system of the device. The device operates on data formed of data granules having associated metadata items, and the bus interface enables communication of both the data granules and the metadata items over the bus between the memory system and the bus interface. The debug access port circuitry further has a plurality of storage elements accessible via the commands issued from the debugger, such that the accesses performed within the memory system via the bus interface are controlled in dependence on the storage elements accessed by the commands. At least one of the storage elements comprises a metadata storage element to store a plurality of metadata items, and the debug access port circuitry is responsive to at least one command from the debugger to perform an access to the memory system in order to transfer at least one of the plurality of metadata items between the metadata storage element and the memory system. This provides an efficient mechanism for enabling a debugger to directly access metadata items within a memory system of the device being debugged.