Systems, apparatuses, and methods for performing debug operations in a secure data center are disclosed. A system includes a computing module coupled to a debug target that includes a processing unit. Prior to being installed in a secure data center, the computing module is preloaded with a signed unlock payload and the debug target is preloaded with a public key of an authentication server. In response to a request to perform debug operations on the debug target in the secure data center, the computing module retrieves and conveys the preloaded signed unlock payload to the debug target. In response to the debug target validating the unlock request with a previously obtained public key of the authentication server, the debug target enters secure debug mode, unlocks the at least one processing unit for debug operations with an unlock vector from the validated unlock payload, and performs debug operations on the processing unit.

An integrated circuit (IC) includes a plurality of intellectual properties (IPs), each of the plurality of IPs includes a test logic. A first memory controller provides user data received from at least one of the plurality of IPs to a first memory in a first operation mode. A scanner gathers debugging data from the test logics of the plurality of IPs in a second operation mode. And a second memory controller receives the debugging data from the scanner and provides the debugging data to the first memory in the second operation mode.

A multitile processing system has an execution unit on each tile, and an interconnect which conducts communications between the tiles according to a bulk synchronous parallel scheme. Each tile performs an on-tile compute phase followed by an intertile exchange phase, where the exchange phase is held back until all tiles in a particular group have completed the compute phase. On completion of the compute phase, each tile generates a synchronisation request and pauses an issue of instructions until it receives a synchronisation acknowledgement. If a tile attains an excepted state, it raises an exception signal and pauses instruction issue until the excepted state has been resolved. However, tiles which are not in the excepted state can continue to perform their on-tile computer phase, and will issue their own synchronisation request in their own normal time frame. Synchronisation acknowledgements will not be received from all of the tiles in the group until the excepted state has been resolved on the tile with the excepted state.

A memory device implements a method of communication over a wireless medium utilizing an antenna embedded in the memory device. The memory device includes a wireless component that authenticates an external device by verifying a credential structure received from the external device over the wireless medium, responds to a request for a secure communication channel from the external device with a symmetric key, and establishes the secure communication channel with the debugging device over the wireless medium, and servicing requests from the external device to access debugging, testing, and diagnostics data of the memory device.

An integrated circuit can include a functional unit and a local debug unit. The local debug unit can include a trace buffer, and the local debug unit is configured to track and store operation information of the functional unit in the trace buffer. The integrated circuit can also include a global debug unit coupled to the local debug unit. The integrated circuit is configured to send a debug reset command to reset the functional unit, without sending the debug reset command to the local debug unit, thereby retaining information stored in the trace buffer. The integrated circuit is also configured to send a power-up reset command to reset the local debug unit and the functional unit, thereby causing the local debug unit to clear the trace buffer.

A connection request is received from a debug UI by a middle tier instance through a first predefined computer port. A connection data request is received from the debug UI by the middle tier instance. Connection data for a debug engine is sent from the middle tier instance to the debug UI and provided to the debug engine from the debug UI. The connection data includes a second predefined computer port of the first computing device. An initial packet is received by the middle tier instance from the debug engine through the second predefined computer port. A unique engine identifier is defined for the debug engine by the middle tier instance and an engine connection confirmation is sent from the middle tier instance to the debug UI indicating that a connection with the debug engine has been established and including the unique engine identifier for the debug engine.

At least one processor core has debug and non-debug modes of operation. Debug control circuitry controls operation of the at least one processor core when in the debug mode. On power up of a given processor core, the core checks a debug status value stored in a debug status storage element. When the debug status value has a first value, a debug connect sequence of messages is exchanged with the debug control circuitry over a debug interface to determine whether the given processor core should operate in the debug mode or the non-debug mode, and the debug status value is set to a second value when it is determined that the given processor core should operate in the non-debug mode. When the debug status value has the second value, the given processor core omits initiating the debug connect sequence and determines that it should operate in the non-debug mode.

A novel system and method for remotely debugging a network device is disclosed. A debug system is used to transmit debug commands over a network to the network device. The network device interprets the debug commands. The processing unit on the network device includes a special debugging mode where it is able to perform special debug operations. This special debugging mode operates at a priority that is lower than that of the network interface so that the network device can still receive network packets while being debugged. The network device also has the ability to generate responses to the debug commands in some embodiments. The concept of wireless debugging can also be applied to multi-core processors as well.

Apparatus and methods are disclosed for initiating instruction block execution using a register access instruction (e.g., a register Read instruction). In some examples of the disclosed technology, a block-based computing system can include a plurality of processor cores configured to execute at least one instruction block. The at least one instruction block encodes a data-flow instruction set architecture (ISA). The ISA includes a first plurality of instructions and a second plurality of instructions. One or more of the first plurality of instructions specify at least a first target instruction without specifying a data source operand. One or more of the second plurality of instructions specify at least a second target instruction and a data source operand that specifies a register.

Systems, apparatuses and methods may provide for receiving one or more debug communications and programming, via a bus, a set of debug registers with debug information corresponding to the one or more debug communications. Additionally, tunnel logic hardware may be instructed to transfer the debug information from the set of debug registers to one or more test access ports of an intelligent device such as a non-volatile memory storage unit having a microcontroller. In one example, if it is detected that debug permission has been granted during a boot process, a control status register may be unlocked. If, on the other hand, the debug permission is not detected during the boot process, the control status register may be locked. Accordingly, an enable bit of the control status register may be used to activate the tunnel logic hardware only if the control status register is unlocked.