An electronic device includes: a first input node configured to receive a dock signal; a second input node configured to receive an activation signal or a deactivation signal; a filter circuit responsive to: (a) the activation signal to activate the filter circuit to block the dock signal; or (b) the deactivation signal to deactivate the filter circuit to pass the dock signal; and an output node configured for coupling to a synchronous I/O interface of an integrated circuit to control operation of the synchronous I/O interface.

Computer-readable media, methods, and systems are disclosed for generating and debugging bytecode for a rule including embedded debug functions. One or more predefined breakpoints are included in the embedded debug functions. When a breakpoint is reached, an execution state for the rule is stored including one or more local variables for the rule. Execution may be resumed by retrieving the stored execution state.

An application debugging method includes receiving identifiers of a plurality of application sub-modules that are input or selected by a user, debugging code blocks of the plurality of application sub-modules based on the identifiers of the plurality of application sub-modules, and presenting a debugging result to the user. The method supports the user to select or input a plurality of to-be-debugged application sub-modules, and debug the plurality of application sub-modules in the production environment.

Disclosed in some examples are methods, systems, devices, and machine-readable mediums that use parallel hardware execution with software co-simulation to enable more advanced debugging operations on data flow architectures. Upon a halt to execution of a program thread, a state of the tiles that are executing the thread are saved and offloaded from the HTF to a host system. A developer may then examine this state on the host system to debug their program. Additionally, the state may be loaded into a software simulator that simulates the HTF hardware. This simulator allows for the developer to step through the code and to examine values to find bugs.

The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to the TAP architecture. In response to a Command signal input, the TAP architecture can perform streamlined and uninterrupted Update, Capture and Shift operation cycles to a target circuit in the device or streamlined and uninterrupted capture and shift operation cycles to a target circuit in the device. The Command signals can be input to the TAP architecture via the devices dedicated TMS or TDI inputs or via a separate CMD input to the device.

In one embodiment, a host processor includes a configuration circuit that, in response to identification of a first device capable of debugging a second device, is to configure a switch to enable device-to-device messaging between the first device and the second device, the device-to-device messaging comprising at least one of debug messaging or test messaging to be communicated without host processor involvement. Other embodiments are described and claimed.

Disclosed herein are a method for debugging a program of many core parallel processors based on code execution and an apparatus for the same. The method, performed by debugger software running on a host processor, includes generating a program execution binary including debug execution code and providing the same to multiple parallel processors, acquiring context data corresponding to the state of a target processor immediately before the debug execution code is executed in the target processor, among the multiple parallel processors, and analyzing the context data and thereby performing debugging of a program executed in the processor in which the debug execution code is executed.

Aspects of the present disclosure provide a processor having: an execution unit configured to execute machine code instructions, at least one of the machine code instructions requiring multiple cycles for its execution; instruction memory holding instructions for execution, wherein the execution unit is configured to access the memory to fetch instructions for execution; an instruction injection mechanism configured to inject an instruction into the execution pipeline during execution of the at least one machine code instruction fetched from the memory; the execution unit configured to pause execution of the at least one machine code instruction, to execute the injected instruction to termination, to detect termination of the injected instruction and to automatically recommence execution of the at least one machine code instruction on detection of termination of the injected instruction.

Exemplary aspects for a specific example concern a radar system having sensor circuitry including multiple radar sensors to provide sensor data via multiple virtual channels and multiple data types, a memory circuit with memory buffers, and a bus-interface circuit to control bus interconnects for bus communications involving a radar signal transmitter and the memory circuit. Radar signals are received and processed, via data acquisition path circuitry in multiple circuit paths and via streams of data in response to and to accommodate the operations of the sensor circuitry. A master controller conveys data, via the bus-interface circuit, to the buffers for the sensor data, and generates selectable-type transactions to be linked in selected ones of the buffers, in response to the data provided from the sensor circuitry and based on the sensor data being provided via different ones of the multiple virtual channels and of the multiple data types.

An industrial monitoring system comprises monitoring devices that are enabled for debugging by a component comprising a first microcontroller unit and a second microcontroller unit. The monitoring device receives a debugging command based on a subscription, on a publish-subscribe communications channel, to events indicative of requests to perform debugging operation. The second microcontroller unit causes the first microcontroller unit to perform the command. Results of performing the command are returned by publishing an event to the publish-subscribe communications channel.