An adapter for connecting an embedded system to a control computer having a standard interface, in particular a network interface, a first subcircuit, and a second subcircuit, the first subcircuit being designed to communicate with the control computer via the standard interface by means of a standard protocol, preferably XCP. The first subcircuit is designed to convert a protocol functionality requested in the standard protocol via the standard interface, out of a set of supported protocol functionalities into the call for one or more elementary functions out of a defined overall set of elementary functions. The first subcircuit is connected to the second subcircuit via an internal interface, wherein the second subcircuit has a programmable computing module which is configured to provide at least one elementary function out of the overall set of elementary functions which can be called up via the internal interface by means of a call.

In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be an embedded-system device. In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be an embedded-system device. The embedded-system device provides to a host of the embedded-system device control of a first serial port controller of the embedded-system device. The embedded-system device further connects a serial port with the first serial port controller. The embedded-system device also determines whether the embedded-system device is in a predetermined condition. The embedded-system device disconnects the serial port from the first serial port controller and connecting the serial port with a second serial port controller when the embedded-system device is in the predetermined condition.

Performing series equivalent scans spanning a plurality of scan technologies in a complex scan topology may be performed by performing shift operations in the complex scan topology while only one branch of the complex scan topology connectivity is enabled, and performing capture and update operations in parallel while scan topology connectivity of two or more of the plurality of scan technologies is enabled.

In accordance with embodiments of the present disclosure, an information handling system may include a host system with information handling resources, a management controller configured to provide out-of-band management of the information handling system, and a debugging circuit. The debugging circuit may receive a plurality of serial data streams from the management controller and the plurality of information handling resources, and provide access to at least a subset of the plurality of serial data streams to a debugging information handling system via a wireless interface.

Determining instruction execution history in a debugger, including: retrieving, from an instruction cache, cache data that includes an age value for each cache line in the instruction cache; sorting, by the age value for each cache line, entries in the instruction cache; retrieving, using an address contained in each cache line, one or more instructions associated with the address contained in each cache line; and displaying the one or more instructions.

Determining instruction execution history in a debugger, including: retrieving, from an instruction cache, cache data that includes an age value for each cache line in the instruction cache; sorting, by the age value for each cache line, entries in the instruction cache; retrieving, using an address contained in each cache line, one or more instructions associated with the address contained in each cache line; and displaying the one or more instructions.

In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be an embedded-system device. In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be an embedded-system device. The embedded-system device provides to a host of the embedded-system device control of a first serial port controller of the embedded-system device. The embedded-system device further connects a serial port with the first serial port controller. The embedded-system device also determines whether the embedded-system device is in a predetermined condition. The embedded-system device disconnects the serial port from the first serial port controller and connecting the serial port with a second serial port controller when the embedded-system device is in the predetermined condition.

Diagnostic operations upon a target apparatus 2 having a target transaction master 8 which initiates memory transactions with one or more target transaction slaves 12, 14, 16 are provided by halting operation of the target transaction master 8 while permitting continued operation within the target apparatus 2 of at least some of the target transaction slaves 12, 14, 16. Opening state data representing an operating state of the target transaction master 8 is transferred to a model transaction master 32. Further operation of the target transaction master 8 is emulated using the model transaction master 32 using the opening state data. Diagnostic operations are performed upon the model transaction master 32. When the model transaction master 32 emulates initiation of a memory transaction with a memory address mapped to one of the target transaction slaves 12, 14, 16, this initiates the memory transaction to be performed with the target apparatus 2. Pages of stored values from the memory address space of the target apparatus 2 may be cached within the emulation.

A hardware debug system includes a target chip comprising one or more target chip registers and one or more target chip ports, wherein at least one of the one or more target chip ports is used as a target chip debug port, and a debug host with one or more debug host ports, wherein at least one of the one or more debug host ports is connected to the target chip debug port via a hardware debug bus, wherein the debug host is configured to load at least one target chip setting into the one or more target chip registers that enables the target chip to boot via the hardware debug port using the hardware debug bus.

A debugging support program causes a computer to execute: a step of extracting, from a module program constituting a sequence program, a first variable assigned to an input to the module program and a second variable assigned to an output from the module program; a step of creating a verification item for verifying operation of the module program, the verification item including a first setting value set for the first variable and a second setting value set for the second variable; a step of verifying operation of the module program based on the verification item; and a step of outputting a result of verifying operation of the module program.