G06F11/3656

Web browser remoting using network vector rendering

Methods, systems, and techniques for application isolation by remote-enabling applications are provided. Example embodiments provide an Adaptive Rendering Application Isolation System (ARAIS), which transparently and dynamically enables applications to run in an isolated execution environment yet be rendered locally in a manner that minimizes the amount of data to be transferred and the latency caused by expensive computation and/or by overburdening available bandwidth by remoting rendering using draw commands over rendering using pixel pushing or other techniques. In one embodiment, the ARAIS includes an orchestrator server which comprises remoting level determination logic and rules engine, pre-computed graphics libraries, connection support logic, data repositories for objects such as a render cache, whitelists, blacklists, client privileges, and application information, and one or more secure containers running remote application instances. These components cooperate to deliver isolation-ready technology to client applications.

DEBUGGING A LIVE STREAMING APPLICATION

A connection can be made to a processing element of a remotely deployed and live streaming application executed by a first data processing system, the processing element containing at least one operator that processes at least one tuple. As the live streaming application is executed, without slowing or modifying data flow of the live streaming application execution to client devices, a copy of the tuple and a memory dump of state data for a state of the operator can be received, and the tuple can be tracked through a call graph. The state data can be loaded into a local instance of the operator loaded into a debugger. At least a portion of the call graph can be presented to a user, and a flow of the tuple through the call graph based on the state data for the operator can be indicated.

Multimodal targets in a block-based processor

Apparatus and methods are disclosed for decoding targets from an instruction and transmitting data to those targets in accordance with a current instruction. Multimodal target hardware is used in conjunction with one or more of the routers so as to route data to an appropriate target. The data can be one or more operands or a predicate and the targets can include operand buffers, broadcast channels, and general registers. In this way, operands, for example, can be directed for use with multiple subsequent instructions, and there are multiple modes for distributing the operands to the multiple instructions.

Extracting transaction level information from a circuit interface
10445219 · 2019-10-15 · ·

Extracting transaction level information from an interface can include tracking transactions of an interface within an integrated circuit (IC) using a plurality of counters within the IC, wherein the counters generate counter data corresponding to the transactions. The method can include capturing signals of the interface as trace data for a trace window using an integrated logic analyzer within the IC, wherein a start of the trace window begins after a start of the tracking of the transactions using the plurality of counters. The method can also include using a host data processing system coupled to the IC, determining transaction level information for the interface using the counter data and the trace data for the trace window.

Pipeline processor data and attribute register, secure emulation logic, gating
10438023 · 2019-10-08 · ·

The present disclosure describes systems and methods for controlling access to secure debugging and profiling features of a computer system. Some illustrative embodiments include a system that includes a processor, and a memory coupled to the processor (the memory used to store information and an attribute associated with the stored information). At least one bit of the attribute determines a security level, selected from a plurality of security levels, of the stored information associated with the attribute. Asserting at least one other bit of the attribute enables exportation of the stored information from the computer system if the security level of the stored information is higher than at least one other security level of the plurality of security levels.

Terminal apparatus, base station apparatus, communication method, and integrated circuit

Provided is a technique related to a terminal apparatus, a base station apparatus, a communication system, a communication method, and an integrated circuit that are capable of efficiently performing device-to-device communication. In a case where a terminal apparatus capable of direct communication between terminal apparatuses starts a timer corresponding to a group index that identifies short-range group communication, to which the terminal apparatus belongs, and the timer expires, switching is performed from a first radio resource allocation method, by which a radio resource to be used for the direct communication is requested to a base station apparatus, to a second radio resource allocation method by which the terminal apparatus selects a radio resource to be used for the direct communication.

Real time terminal for debugging embedded computing systems
10437694 · 2019-10-08 ·

One or more circular debug buffers can allow terminal output data to be provided from the target system to a host without halting the target system or causing significant delays. One or more circular debug buffers may also allow input (such as keyboard input) to be provided from the host to the target without halting the target system or causing significant delays. Accordingly, communications between the target and host may be performed in real time or near real time. These communications may be used for debugging purposes or more generally, for any purpose, including purposes unrelated to debugging.

DEBUGGING AN EXECUTABLE CONTROL FLOW GRAPH THAT SPECIFIES CONTROL FLOW
20190303271 · 2019-10-03 ·

A computer-implemented method for debugging an executable control flow graph that specifies control flow among a plurality of functional modules, with the control flow being represented as transitions among the plurality of functional modules, the computer-implemented method including: specifying a position in the executable control flow graph at which execution of the executable control flow graph is to be interrupted; wherein the specified position represents a transition to a given functional module, a transition to a state in which contents of the given functional module are executed or a transition from the given functional module; starting execution of the executable control flow graph in an execution environment; and at a point of execution representing the specified position, interrupting execution of the executable control flow graph; and providing data representing one or more attributes of the execution environment in which the given functional module is being executed.

DEBUG CONTROLLER CIRCUIT
20190303268 · 2019-10-03 · ·

A circuit arrangement includes one or more input buffers disposed on a system-on-chip (SoC) and configured to receive and store streaming debug packets. One or more response buffers are also disposed on the SoC. A transaction control circuit is disposed on the SoC and is configured to process each debug packet in the one or more input buffers. The processing includes decoding an operation code in the debug packet, and determining from an address in the debug packet, an interface circuit of multiple interface circuits to access a storage circuit in a subsystem of multiple sub-systems on the SoC. The processing further includes issuing a request via the interface circuit to access the storage circuit according to the operation code, and storing responses and data received from the interface circuits in the one or more response buffers.

DEBUGGING OF ACCELERATOR CIRCUIT FOR MATHEMATICAL OPERATIONS USING PACKET LIMIT BREAKPOINT
20240143483 · 2024-05-02 · ·

Embodiments of the present disclosure relate to debugging of an accelerator circuit using a packet limit breakpoint. A vector circuit reads a subset of instruction packets from an instruction memory and receives a portion of input data from a data memory corresponding to the subset of instruction packets. The vector circuit executes a set of vector operations in accordance with multiple instruction packets from the subset using data from the received portion of input data identified in the multiple instruction packets to generate output data. A program counter control circuit coupled to the instruction memory triggers a breakpoint in a program stored in the instruction memory causing the accelerator circuit to stop executing remaining instruction packets in the program following the multiple instruction packets responsive to a number of instruction packets executed in the program from a time instant of an event reaching a predetermined number.