A remote debug session for a server group is provided. A server group including multiple servers that perform workload sharing receives a request to debug code executed at the server group. The code is executed on behalf of a client of a database associated with the server group. At least one of the servers of the group initiates a debugging session and establishes a communication connection with the client. The server group maintains the connection open with the client for the duration of the debugging session. Subsequent requests related to the debug session can be handled in a number of ways by the server group, and all communication to the client about processing the requests is through the connection.

An integrated circuit device comprises: a first power domain (100) including a processor (2) and non-volatile memory (10) connected to the processor; and a second power domain (200) including an access port (12) connected to the non-volatile memory. The access port is further connected to an electrical interface (4) suitable for connection to a debugger.

The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to the TAP architecture. In response to a Command signal input, the TAP architecture can perform streamlined and uninterrupted Update, Capture and Shift operation cycles to a target circuit in the device or streamlined and uninterrupted capture and shift operation cycles to a target circuit in the device. The Command signals can be input to the TAP architecture via the devices dedicated TMS or TDI inputs or via a separate CMD input to the device.

A method includes associating an associated processor address register with a predetermined operation, invoking an instruction including a reference to a referenced processor address register, and, if the referenced processor address register is the associated processor address register, performing the predetermined operation.

The present disclosure describes systems and methods for controlling access to secure debugging and profiling features of a computer system. Some illustrative embodiments include a system that includes a processor, and a memory coupled to the processor (the memory used to store information and an attribute associated with the stored information). At least one bit of the attribute determines a security level, selected from a plurality of security levels, of the stored information associated with the attribute. Asserting at least one other bit of the attribute enables exportation of the stored information from the computer system if the security level of the stored information is higher than at least one other security level of the plurality of security levels.

Apparatus and methods are disclosed for controlling instruction flow in block-based processor architectures. In one example of the disclosed technology, an instruction block address register stores an index address to a memory storing a plurality of instructions for an instruction block, the indexed address being inaccessible when the processor is in one or more unprivileged operational modes, one or more execution units configured to execute instructions for the instruction block, and a control unit configured to fetch and decode two or more of the plurality of instructions from the memory based on the indexed address.

An energy-interference-free debugger is disclosed for debugging software resident on energy-harvesting target devices, which may periodically lose power and therefore exhibit intermittent execution of the software. The debugger is implemented as a combination of hardware and software and provides, in addition to the traditional debugging tools, the ability to monitor and modify the energy level on the target device, the ability to set breakpoints based on the energy level on the target device, and the ability to isolate portions of the code executing on the target device from energy-related failure during debugging. The debugger is able to remain isolated from intermittent power in passive mode and to create an illusion of an untouched energy reservoir in active mode.

An embodiment provides a memory system connectable to a host device. The memory system includes a host interface configured to receive a read command and a write command and a first non-volatile memory. In addition, the memory system includes a debug unit configured to collect debugging information when a processor executes firmware. The debug unit is capable of outputting the debugging information to a buffer area of the host device through the host interface.

A debugging support program causes a computer to execute: a step of extracting, from a module program constituting a sequence program, a first variable assigned to an input to the module program and a second variable assigned to an output from the module program; a step of creating a verification item for verifying operation of the module program, the verification item including a first setting value set for the first variable and a second setting value set for the second variable; a step of verifying operation of the module program based on the verification item; and a step of outputting a result of verifying operation of the module program.

According to an embodiment, a system is provided that includes a debugging tool and an application board. The debugging tool includes a serial wire debug (SWD) host coupled to a single signal debug port (SSDP) host. The application board includes an SWD target coupled to an SSDP target. The SWD target is configured to communicate SWD signals with the SWD host. The SSDP target is configured to encode the SWD signals to SSDP signals for communication over a Controller Area Network (CAN) Bus between the application board and the debugging tool. The SSDP signals are pulse-width modulation (PWM) encoded signals of the SWD signals. An SWD clock signal generated by the SWD host is the carrier signal for the PWM encoded signals. The SSDP target is configured to decode the SSDP signals received from the SSDP host over the CAN Bus to the SWD signals.