According to one general aspect, an apparatus may include an interconnect bus, an interconnect-to-debug bus interface, and a debug bus. The interconnect bus may be configured to connect and manage combinatorial logical blocks during normal operation of a processor and operate synchronous to a core clock. The interconnect-to-debug bus interface may be configured to translate communications between the interconnect bus and the debug bus. The debug bus may include a plurality of debug wrapper circuits arranged in a daisy chain for unidirectional communication, and configured to operate synchronous to the core clock. Each of the plurality of debug wrapper circuits may be configured to: identify if the respective debug wrapper circuit is activated by the debug bus, receive a non-invasive input from a respective combinatorial logic block, and place the non-invasive input from the respective combinatorial logic block on the debug bus.

In one embodiment, a clock-gating system for a pipeline includes a clock-gating device configured to gate or pass a clock signal to the pipeline, and a clock controller. The clock controller is configured to track a number of input packets at an input of the pipeline, to track a number of output packets at an output of the pipeline, to determine whether to gate or pass the clock signal based on the number of the input packets and the number of the output packets, to instruct the clock-gating device to pass the clock signal if a determination is made to pass the clock signal, and to instruct the clock-gating device to gate the clock signal if a determination is made to gate the clock signal.

A processor includes an innovation engine, a non-volatile memory, a reserved device, one or more user-defined devices, and logic to execute the user-defined devices. The processor also includes a debug engine with logic to monitor the processor for trigger conditions and record data associated with the trigger conditions. The innovation further includes logic to selectively load the debug engine.

Techniques for secure remote debugging of SoCs are described. The SoC includes an intellectual property (IP) block, a microcontroller, and a fabric coupled to the IP block and the microcontroller. The IP block transmits, via the fabric, information regarding events within the IP block to the microcontroller. The microcontroller executes firmware including a network stack and a remote debugger program. Using the firmware, the microcontroller provides the event information to a device external to the SoC.

A remote debug session for a server group is provided. A server group including multiple servers that perform workload sharing receives a request to debug code executed at the server group. The code is executed on behalf of a client of a database associated with the server group. At least one of the servers of the group initiates a debugging session and establishes a communication connection with the client. The server group maintains the connection open with the client for the duration of the debugging session. Subsequent requests related to the debug session can be handled in a number of ways by the server group, and all communication to the client about processing the requests is through the connection.

A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

A connection can be made to a processing element of a remotely deployed and live streaming application executed by a first data processing system, the processing element containing at least one operator that processes at least one tuple. As the live streaming application is executed, without slowing or modifying data flow of the live streaming application execution to client devices, a copy of the tuple and a memory dump of state data for a state of the operator can be received, and the tuple can be tracked through a call graph. The state data can be loaded into a local instance of the operator loaded into a debugger. At least a portion of the call graph can be presented to a user, and a flow of the tuple through the call graph based on the state data for the operator can be indicated.

A data processing apparatus is provided having a hierarchy of layers comprising at least two data processing layers, each data processing layer configured to receive data and to generate processed data for passing to a next lower layer in said hierarchy, according to a protocol specific to that data processing layer. Each data processing layer is configured intermittently to add synchronization information to its processed data, the synchronization information providing semantic information required to interpret the processed data. Each data processing layer is further configured to output its synchronization information in response to a synchronization request signal received from a lower layer in said hierarchy, and at least one data processing layer is configured, when outputting its synchronization information, to issue its synchronization request signal to a higher layer in the hierarchy.

An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.

Systems and methods for providing a debugging interface for inserted elements in a resource are provided. One method includes detecting a trigger for a request to provide a debugging interface for a webpage, the webpage including a content interface configured to display third party content items. The method further includes transmitting the request for the debugging interface to a remote device, and receiving a script representing the debugging interface from the remote device. The method further includes inserting the debugging interface into the webpage by injecting the script into data of the webpage during loading of the webpage. The method further includes detecting a characteristic of at least one of the webpage, the content interface, or the remote device; and generating debugging information using the detected characteristic. The method further includes providing the debugging information in the debugging interface.