Embodiments of recovering data in computing devices and associated methods of operations are disclosed therein. In one embodiment, a method includes receiving a failure notification indicating that a core of a main processor is experiencing a catastrophic failure causing the core unable to execute instructions. In response, a flush command can be issued to an uncore of the processor via a debug port instructing the uncore to copy any data currently residing in a processor cache of the main processor to a volatile memory. The method further includes issuing a self-refresh command causing the volatile memory to enter a self-refresh mode in which the data copied from the processor cache is maintained and unmodifiable by the main processor during a reset of the main processor.

A tester instruction generation unit generates a tester instruction for terminals of a plurality of devices connected to a tester based on an instruction of a user program and causes an instruction storage unit to store the tester instruction. A transfer mode setting unit sets a transfer mode to either a successive transfer mode or a batch transfer mode, based on the number of tester instructions in the instruction storage unit or an instruction of the user program. A transfer control unit transmits the tester instruction in the instruction storage unit to the tester in accordance with the set transfer mode.

SoundWire-based embedded debugging in an electronic system is provided. In this regard, in one aspect, a SoundWire slave circuit receives a SoundWire data input signal over a SoundWire bus including two physical wires. The SoundWire data input signal includes a plurality of debug configuration bits in assigned SoundWire bitslots. The SoundWire slave circuit generates a plurality debug input bits required for debugging the SoundWire slave circuit based on the debug configuration bits received in the assigned SoundWire bitslots. In another aspect, the SoundWire slave circuit returns a SoundWire data output signal, which includes a debug output bit in an assigned SoundWire bitslot, over the SoundWire bus. By receiving debugging configurations and returning debugging results over the SoundWire bus, it is possible to debug the SoundWire slave circuit with a reduced number of physical pins, thus helping to reduce the overall pin count and footprint of the electronic device.

Disclosed herein is method and system for debugging target automotive applications in an ECU of an automobile. A debug agent implemented in the ECU collects debugging information related to the target automotive applications and transmits it to an external computing system. The external computing system generates debugging instructions corresponding to debugging activities associated with the target automotive applications based on the debugging information and transmits the encoded debugging instruction to the debug agent. The debug agent decodes and forwards the decoded debugging instructions to a debug server in the ECU, which performs the debugging activities by executing the decoded debugging instructions, thereby debugging the target automotive applications. In an embodiment, the debug agent collects all vital information related to target automotive applications, hence, providing an effective method of diagnosing the target automotive applications. Further, the method also eliminates the need for taking the ECU out of the automobile during debugging.

A hardware debug system includes a target chip comprising one or more target chip registers and one or more target chip ports, wherein at least one of the one or more target chip ports is used as a target chip debug port, and a debug host with one or more debug host ports, wherein at least one of the one or more debug host ports is connected to the target chip debug port via a hardware debug bus, wherein the debug host is configured to load at least one target chip setting into the one or more target chip registers that enables the target chip to boot via the hardware debug port using the hardware debug bus.

A processing device comprises a debug port controller to monitor operations of the processing device to determine whether the processing device is operating in a first mode or a second mode and to collect trace information comprising operating characteristics of the processing device. The processing device further comprises a display engine logic to process display data for output to a display device. In addition, the processing device comprises a display engine interface to provide, to a plurality of existing platform connectors, the display data from the display engine logic when the processing device is operating in the first primary mode and the trace information from the debug port controller when the processing device is operating in the second mode as determined by the debug port controller.

Systems, computer program products, and methods are described herein for implementing a code debugger platform in a virtual environment. The system is configured to authenticate a plurality of users via an authentication portal and initialize an instance of a virtual environment for each of the plurality of users. The system is configured to extract a plurality of computer instructions, and display, in the virtual environment, a debugging platform of an integrated development environment, the debugging platform configured to receive the plurality of computer instructions and receive input from at least one of the plurality of users, and initiate a debugging protocol. The debugging protocol may include a breakpoint in at least one of the plurality of computer instructions, wherein the breakpoint is received as an input from the at least one of the plurality of users.

An apparatus includes a processor circuit that includes a memory circuit, one or more processor cores, and a debug circuit. The debug circuit may be configured, in response to activation of a trace mode to record information indicative of instructions executing on the one or more processor cores, to write a trace data stream to the memory circuit that includes trace data collected on the instructions executing on the one or more processor cores. In response to a particular instruction within one of the processor cores specifying a write of a data value to an architecturally visible trace register, the debug circuit may be further configured to output the data value to the trace data stream as part of executing the particular instruction.

This application is directed to communicating telemetry and debugging data of a memory system using optical signals. An enclosed memory device has an optical indicator and receives a data request. In response to the data request, the enclosed memory device obtains internal activity data stored in the memory device, encodes the internal activity data into an electrical signal, and drives the optical indicator with the electrical signal to generate a visible light signal carrying the internal activity data. In some embodiments, the enclosed memory device includes a solid-state drive. In some embodiments, the internal activity data includes telemetry data stored by the enclosed memory device while the memory device is processing a sequence of memory access requests including at least one of a read request and a write request.

This application is directed to communicating telemetry and debugging data of a memory system using optical signals. An enclosed memory device has an optical indicator and receives a data request. In response to the data request, the enclosed memory device obtains internal activity data stored in the memory device, encodes the internal activity data into an electrical signal, and drives the optical indicator with the electrical signal to generate a visible light signal carrying the internal activity data. In some embodiments, the enclosed memory device includes a solid-state drive. In some embodiments, the internal activity data includes telemetry data stored by the enclosed memory device while the memory device is processing a sequence of memory access requests including at least one of a read request and a write request.