Systems and methods for secure booting of secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in a PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in a non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD to the configuration engine. The secure PLD is configured to retrieve a pre-authentication status associated with the configuration image from the NVM, determine or verify the retrieved pre-authentication status associated with the configuration image includes a valid status, and boot the PLD fabric of the secure PLD using the configuration image.

Systems and methods for provisioning secure programmable logic devices (PLDs) are disclosed. An example secure PLD provisioning system includes an external system comprising a processor and a memory and configured to be coupled to a secure PLD through a configuration input/output (I/O) of the secure PLD. The external system is configured to generate a locked PLD comprising the secure PLD based, at least in part, on a request from a secure PLD customer, wherein the request from the secure PLD customer comprises a customer public key; and to provide a secured unlock package for the locked secure PLD. The external system may also be configured to provide an authenticatable key manifest comprising a customer programming key token and a corresponding programming public key associated with the locked secure PLD, wherein the authenticatable key manifest is signed using a programming private key generated by the locked secure PLD.

Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device performs operations comprising receiving a memory access command; responsive to detecting that the memory access command satisfies a trigger condition, recording, in a set of registers, data associated with a plurality of events performed by processing the memory access command; and responsive to detecting that the set of registers comprises the data, disabling write operations on the set of registers.

The disclosure is directed to methods and systems for improving interactions with a Large Language Model (LLM). An artificial intelligence system (AIS) can receive user inputs via a graphical user interface indicating a task to be performed by the LLM, one or more tools which may be accessed by the AIS in response to tool calls from the LLM, and an output schema for structuring a format of a response from the LLM. The AIS can generate a prompt for the LLM based on the user input. The prompt can include indications of the one or more tools, one or more example tool operations, the task to be performed, and an indication of the output schema. The AIS can include a debugging application or module enabling rich debugging of language model interactions in a single view.

An integrated circuit (IC) device includes functional circuitry and data capture circuitry that stores a state of the functional circuitry in a buffer and outputs contents of the buffer to an external device based on a trigger. An embedded processor interacts with the functional circuitry based on a computer program, and initiates the trigger. The processor may initiate the trigger at a selectable break-point of the computer program and/or based on data generated by the functional circuitry. The processor may also output corresponding states of variables managed by the processor. The processor may initiate the trigger by asserting a predetermined value on a communication path between the processor and the functional circuitry, or over another communication path (e.g., an AXI debug hub) between the processor and the data capture circuitry. The processor may monitor/control the data capture circuitry through an API.

Circuits, systems and methods are provided. A circuit includes a subsystem, an interface, and a debugger. The interface includes power processing and management (PPM) circuitry coupled to the subsystem, and arbitration logic coupled to the PPM circuitry. In operation, the debugger issues a debug request to the arbitration logic to perform a debug operation on the subsystem, and, in response to the debug request, the arbitration logic provides an interrupt associated with the subsystem to the PPM circuitry. The PPM circuitry, in response to the interrupt and a determination that the subsystem is OFF, powers on the subsystem and provides a notification to the arbitration logic indicating that the subsystem is ON. The PPM circuitry also receives a notification from the arbitration logic that the debug operation related to the debug request is complete, and powers off the subsystem in response to that notification.

A real-time debugger implementation maintains and manages multiple debug contexts allowing developers to interact with real-time applications without breaking the system in which the debug application is executing. The debugger allows multiple debug contexts to exist and allows break points in real-time and non-real-time code portions of one or more applications executing on a debug enabled core of a processor. A debug monitor function may be implemented as a hardware logic module on the same integrated circuit as the processor. Higher priority interrupt service requests may be serviced while otherwise maintaining a context for the debug session (e.g., stopped at a developer defined breakpoint). Accordingly, the application developer executing the debugger may not have to be concerned with processing occurring on the processor that may be unrelated to the current debug session.

A method includes executing, by a processor, a first code section having a first priority; encountering, by the processor, during the executing of the first code section, a breakpoint; receiving, by the processor, while at the breakpoint, an interrupt associated with a second code section, the interrupt having a second priority that is higher than the first priority; servicing, by the processor, the interrupt including executing the second code section; receiving a debug access request associated with the breakpoint during the servicing of the interrupt; blocking servicing of the debug access request until servicing of the interrupt is completed; and servicing, by the processor, the debug access request after completing service of the interrupt.

An arrangement for disabling a configuration of a first programmable hardware component, having the first programmable hardware component, a second programmable hardware component, and a switching element. The first programmable hardware component has a configuration interface for configuring a logic of the first programmable hardware component, a data interface for communication of the logic with the second programmable hardware component, a debugging interface for debugging and configuring the logic, and a configuration monitoring interface for signaling a configuration process of the logic. The switching element is designed and connected to the debugging interface such that access to the debugging interface during a configuration process of the logic can be disabled.

Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values.