Systems, apparatuses and methods may provide for receiving one or more debug communications and programming, via a bus, a set of debug registers with debug information corresponding to the one or more debug communications. Additionally, tunnel logic hardware may be instructed to transfer the debug information from the set of debug registers to one or more test access ports of an intelligent device such as a non-volatile memory storage unit having a microcontroller. In one example, if it is detected that debug permission has been granted during a boot process, a control status register may be unlocked. If, on the other hand, the debug permission is not detected during the boot process, the control status register may be locked. Accordingly, an enable bit of the control status register may be used to activate the tunnel logic hardware only if the control status register is unlocked.

Methods for invasive debug of a processor without processor execution of instructions are disclosed. As a part of a method, a memory mapped I/O of the processor is accessed using a debug bus and an operation is initiated that causes a debug port to gain access to registers of the processor using the memory mapped I/O. The invasive debug of the processor is executed from the debug port via registers of the processor.

The present application relates to a flash memory controller and a method of operating thereof. A system bus interface is provided to interface with a system bus and a debug bus interface is provided to interface with a debug bus. A flash access control block is provided to perform storage I/O operations on a flash memory array. A debug control block is provided to monitor debug related information. The flash memory controller is configured to selectively operate in one or storage operating mode or debug operating mode. In the debug operating mode: the storage control block is configured to serve only read data access requests; and the debug control block is configured to store trace messages in an allocated part of the storage resources of the flash memory controller in response to trace events. The trace messages are generated on the basis of the monitored debug related information.

Target device monitoring systems and methods are presented. In one embodiment, a host emulation target device control method includes receiving high level express interface direction to change a design element value. The design element values are associated with an operating target device. Design element values corresponding to the direction are created. The design element values are also forwarded to the operating target device in real time.

The present disclosure describes systems and methods for controlling access to secure debugging and profiling features of a computer system. Some illustrative embodiments include a system that includes a processor, and a memory coupled to the processor (the memory used to store information and an attribute associated with the stored information). At least one bit of the attribute determines a security level, selected from a plurality of security levels, of the stored information associated with the attribute. Asserting at least one other bit of the attribute enables exportation of the stored information from the computer system if the security level of the stored information is higher than at least one other security level of the plurality of security levels.

Techniques for secure remote debugging of SoCs are described. The SoC includes an intellectual property (IP) block, a microcontroller, and a fabric coupled to the IP block and the microcontroller. The IP block transmits, via the fabric, information regarding events within the IP block to the microcontroller. The microcontroller executes firmware including a network stack and a remote debugger program. Using the firmware, the microcontroller provides the event information to a device external to the SoC.

Provided are a multichip debugging method and a multichip system adopting the same. The multichip system includes: a first chip including a first debugging port and first identification (ID) information, a second chip including a second debugging port and second ID information, and a test access port (TAP) electrically connected to the first debugging port and the second debugging port and configured to connect to a test apparatus via the TAP.

A method for listing optimal machine instances in a computing environment based on user context is provided. The method includes receiving a task request based on a first task to be performed within the computing environment, identifying one or more similar tasks by comparing metadata for the first task to metadata for a plurality of other tasks based on a classification analysis, selecting the one or more similar tasks based on a result from the classification analysis exceeding a predetermined confidence level, and generating a list of one or more previous machine instances corresponding to the one or more similar tasks. The list of previous machine instances is associated with instructions to commence the previous machine instances. The plurality of other tasks include previous tasks performed within the computing environment on corresponding previous machine instances. The machine instances may include a virtual machine (VM) instance or a physical machine instance.

A method for listing optimal machine instances in a computing environment based on user context is provided. The method includes receiving a task request based on a first task to be performed within the computing environment, identifying one or more similar tasks by comparing metadata for the first task to metadata for a plurality of other tasks based on a classification analysis, selecting the one or more similar tasks based on a result from the classification analysis exceeding a predetermined confidence level, and generating a list of one or more previous machine instances corresponding to the one or more similar tasks. The list of previous machine instances is associated with instructions to commence the previous machine instances. The plurality of other tasks include previous tasks performed within the computing environment on corresponding previous machine instances. The machine instances may include a virtual machine (VM) instance or a physical machine instance.

In some aspects, the techniques described herein relate to a device including: a debug port; a trusted execution environment (TEE), the TEE storing a public key; and a controller, the controller configured to: receive a command to access the debug port, the command including a signature generated using a private key corresponding to the public key; provide the command to the TEE, wherein the TEE validates the command by validating the signature using the public key to obtain a validation result; and modify access to the debug port based on the validation result.