Methods, systems, and devices for error detection event mechanism are described. The memory system may identify a fault condition and transmit, to a host system, a message indicating a first indication that the fault condition exists at the memory system. In some cases, the memory system may set, in a register of the memory system, a second indication indicating a type of the fault condition based on identifying the fault condition. The memory system may perform a recovery procedure based on the first indication and the second indication.

Integrated circuits may include registers that store register states. Only a subset of the registers may store critical register states. The subset of registers may be specially demarcated, such as using synthesis directions in the hardware description, and may be coupled to dedicated extraction/loading circuitry. The extraction/loading circuitry may be implemented using soft or hard logic or can leverage existing programming or debugging circuitry on a programmable integrated circuit. The extraction/loading mechanism may also be implemented using multiplexers and associated control circuitry, scan chain circuitry, a memory-mapped interface, a tool-instantiated or user-instantiated finite state machine, or external memory interface logic. Accessing critical register states in this way can help improve efficiency with live migration events, debugging, retiming, and other integrated circuit operations.

Mechanisms are provided for recovering a worker node that is in a not ready state. A first worker node of a cluster is configured with a first debug utility that comprises a debug node agent that monitors an operating state of the first worker node. In response to the debug node agent detecting the first worker node being not ready, the debug node agent sends a request to a debug proxy of a second debug utility associated with a second worker node that is in a ready state, to create a debug worker node for the first worker node based on a customer resource definition from a master node, where the debug worker node has a minimum configuration for handling debug commands. The debug commands from a user are processed via the debug worker node to return the first worker node to a ready state.

In general, trace and debug logic should not be affected by all functional or destructive resets of a processing system. However, certain events, such as power supply related events may be utilized to reset the trace and debug logic since the trace and debug logic may cease correct operation if the provided power supply is insufficient. In addition, it may be beneficial for a debugger to initiate requests to reset trace and debug logic. Further, fault triggers from critical path monitors may be candidates as a source of reset for the trace and debug circuitry. For example, when critical path monitors trigger a fault, the fault may be from the logic associated with either trace and debug logic or the logic which is being debugged or traced. As such, in some instances both trace and debug circuitry and the processing system may be inoperable and may need to be reset.

A method for blocking external debugger application from analysing code of software program installed on computing device. The method including initializing software program including an application program and an internal debugger application. The software program, upon initialization thereof, instructs internal debugger application to load application program in internal debugger application. The internal debugger application is configured to utilize kernel resources of an operating system of the computing device. The method includes executing internal debugger application to set one or more break-points in code of application program to define execution path for code of application program, executing application program as per defined execution path for code thereof, stopping execution of code of application program upon reaching any of one or more break-points therein, and handing control to internal debugger application to provide an address for next instruction to be executed in defined execution path for code of application program.

A server management method, apparatus and system, an electronic device and a non-transitory readable storage medium are provided by the present application. The server management system includes a target physical interface, a baseboard management controller (BMC) monitoring management chip, and a state control switcher, wherein the BMC monitoring management chip includes a serial port function interface and a network function interface; the BMC monitoring management chip is connected to the target physical interface through the serial port function interface, and the target physical interface operates in a serial port management mode; the BMC monitoring management chip is connected to the target physical interface through the network function interface, and the target physical interface operates in a network management mode.

Embodiments of the present disclosure relate to debugging of an accelerator circuit using a packet limit breakpoint. A vector circuit reads a subset of instruction packets from an instruction memory and receives a portion of input data from a data memory corresponding to the subset of instruction packets. The vector circuit executes a set of vector operations in accordance with multiple instruction packets from the subset using data from the received portion of input data identified in the multiple instruction packets to generate output data. A program counter control circuit coupled to the instruction memory triggers a breakpoint in a program stored in the instruction memory causing the accelerator circuit to stop executing remaining instruction packets in the program following the multiple instruction packets responsive to a number of instruction packets executed in the program from a time instant of an event reaching a predetermined number.

An example system includes execution circuitry disposed within a first power domain; a sub-system to selectively operate to perform operations on the system and that is disposed within a second power domain that is separate from the first power domain; power control circuitry coupled to the sub-system; and detection circuitry coupled to the power control circuitry. The power control circuitry is configured to cause power to be supplied to the sub-system when the detection circuitry detects that the external component is coupled to the system, and configured to disable power supply to the sub-system when the detection circuitry detects that the external component is not coupled to the system.

An integrated-circuit chip and method of operating said chip is provided. The integrated-circuit chip includes multiple processors, a system memory and a main system bus for carrying data between each of the processors and the system memory. The chip also has debug logic, a debug port for communicating with the debug logic from outside the chip and a debug connection that connects the debug logic to the main system bus. A power management system is also included for controlling the power supplied to each of a number of power domains on the chip. The debug logic and each of the processors are in different respective power domains. The debug logic is configured to send a debug instruction to any of the processors. The debug instruction is communicated over the debug connection and over the main system bus.

A system configures a debugger interface for interacting with a plurality of debugging processes that are configured to debug scripting language programs. Each debugging process runs on an execution engine. A scripting language program can be debugged across the execution engines. The system receives debug commands, which are sent to a first execution engine that debugs a first section of a scripting language program. Debug information from the first execution engine describing debugging of the first section is sent to the debugger interface for display. The system receives debug instructions from the first execution engine to debug a second section of the scripting language program, and the system switches debugging of the scripting language program to a second execution engine. The system may continue to switch debugging between execution engines based on the receipt of new debug instructions until the entirety of the scripting language program has been debugged.