A method for monitoring the free space of a stack of a microcontroller during the execution of a process using spaces of the stack from a start address to an end address of the stack, in which the method includes: in a prior step, writing N keys in the stack at N addresses of the stack, the memory space between two consecutive keys decreasing in a direction from the start address to the end address of the stack; and, in a step of executing the process, saving the address of the current key, corresponding to the address of the existing key, among the N keys, that is closest to the stack start address.

A method for constructing a persistent memory index in a non-uniform memory access architecture includes: maintaining partial persistent views in a persistent memory and maintaining a global volatile view in a DRAM; an underlying persistent memory index processing a request in a foreground thread when cold data is accessed; when hot data is accessed, reading a key-value pair for a piece of hot data in the global volatile view in response to a query operation carried in the request, and in response to an insert/update/delete operation carried in the request, updating a local partial persistent view and the global volatile view; and in response to a hotspot migration, a background thread generating new partial persistent views and a new global volatile view, and recycling the partial persistent views and the global volatile view for old hot data into the underlying persistent memory index.

An integrated circuit includes a compression accelerator to process a request from software to compress source data into an output file. The compression accelerator includes early-abort circuitry to provide for early abort of compression operations. In particular, the compression accelerator uses a predetermined sample size to compute an estimated size for a portion of the output file. The sample size specifies how much of the source data is to be analyzed before computing the estimated size. The compression accelerator also determines whether the estimated size reflects an acceptable amount of compression, based on a predetermined early-abort threshold. The compression accelerator aborts the request if the estimated size does not reflect the acceptable amount of compression. The compression accelerator may complete the request if the estimated size reflects the acceptable amount of compression. Other embodiments are described and claimed.

Dynamically coalescing atomic memory operations for memory-local computing is disclosed. In an embodiment, it is determined whether a first atomic memory access and a second atomic memory access are candidates for coalescing. In response to a triggering event, the atomic memory accesses that are candidates for coalescing are coalesced in a cache prior to requesting memory-local processing by a memory-local compute unit. The atomic memory accesses may be coalesced in the same cache line or atomic memory accesses in different cache lines may be coalesced using a multicast memory-local processing command.

A mapping information management method, a memory storage device, and a memory control circuit unit are provided. The method includes: receiving a write command instructing storing of first data from a host system; storing the first data to a rewritable non-volatile memory module according to the write command; updating mapping information corresponding to the storing of the first data; storing the mapping information to the rewritable non-volatile memory module; generating assistant information according to first part information of the mapping information, where the assistant information is not stored into the rewritable non-volatile memory module; and transmitting second part information of the mapping information and the assistant information to the host system to provide information related to the storing of the first data.

A non-transitory computer-readable recording medium storing an acceleration test program for causing a computer to execute a process, the process includes selecting a cooperation application that operates in cooperation with a test target application that is a target application of an acceleration test by accelerating an operation of an application, determining an acceleration degree of an operation in an acceleration mode in which an operation of an application is accelerated in comparison to a normal mode, and disabling an acceleration of an operation of a non-cooperation application that does not cooperate with the test target application during an acceleration of operations of the test target application and the cooperation application based on the acceleration degree.

A method for reprogramming data of a software function executed by an execution core and a security core, the data being present in two physically separate non-volatile memories, each managed by one of the execution or security cores, including the following steps: upon receiving a reprogramming request, a second value is stored in a first Boolean, determining whether the first Boolean is equal to the second value and if a second Boolean is equal to a first value, and if affirmative; an execution core is made to emit at a reinitialization request via a bidirectional communication channel towards a security core and a request to initialize a portion of the first non-volatile memory towards the set of functions for managing the non-volatile memory by an execution core; a second value is stored in the second Boolean; it is determined whether a predetermined reprogramming event has taken place, and if affirmative, the first value is stored in the first Boolean, while keeping the second value in the second Boolean, and each security core is made to emit a request to write predetermined stored values to the set of functions for managing the memory associated with the non-volatile memory managed by the security core.

A method of operating a multi-bank storage device includes transmitting a write command including stream identification information to the multi-bank storage device, and allocating at least one bank, in which data associated with the write command is to be stored, from among a plurality of banks in the multi-bank storage device, based on striping size information included within the stream identification information. Upon allocation, the data is written into the allocated at least one bank.

Provided are a non-volatile dual inline memory module (NVDIMM) supporting a DRAM cache mode and an operation method of the NVDIMM. The NVDIMM includes a DRAM chip, an NVM chip, and a controller that controls the DRAM chip to operate as a cache memory of the NVM chip. The controller sends a read command to the DRAM chip with reference to a cache address of data requested to be written from a host to the NVM chip, and sends a write command to the NVM chip with reference to an address of the data requested to be written at a time point when a read latency (RL) of the DRAM chip and a write latency (WL) of the NVM chip coincide with each other.

A memory-referent instruction is executed to calculate a target effective address (EA) of a corresponding memory-referent request. An array entry in an upper level cache is allocated, and the EA is specified in a corresponding EA directory entry. While in-flight, the memory-referent request is buffered in a queue in association with a pointer to the entry in the EA directory. Based on receiving a translation invalidation request requesting invalidation of an address translation in a translation structure, the processor core walks the EA directory, determines the EA in the entry matches an address range specified by the translation invalidation request, and, based on the match, precisely marks the memory-referent request using the pointer to the EA directory entry. Based on the marking, the translation invalidation request is permitted to complete with reference to the processor core only after the memory-referent request has drained from the processing unit.